Die Attach Pick Error Detection Using Check GEC Skeleton
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Solution Overview
Problem
Conventional semiconductor wafer processing systems face challenges in detecting pick and place index and map shift errors during the die attachment process, leading to potential misalignment and incorrect mounting of good or bad dice, which can result in scrapping entire assembly lots or requiring costly retesting.
Innovation Solution
The implementation of a predefined set of check Good Electrical Chips (GECs) or Check GECs, preselected based on a specific algorithm, to create a known check skeleton on the wafer, allowing for reliable verification of pick errors by ensuring accurate alignment and minimizing the probability of machine alignment errors during processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reference die alignment is performed only at the start of each wafer, then the alignment process is simple and fast, but any error that occurs after alignment is undetectable and allows bad die to be mounted
Solution Approach 1:
Check GECs are preselected based on a specific algorithm before the pick and place process begins. These check GECs are intentionally left in place to serve as verification points during processing, allowing alignment errors to be detected without slowing down the overall workflow
Solution Approach 2:
The system implements continuous feedback by verifying the presence of check GECs at predetermined locations during the pick and place process. If a check GEC is missing or misplaced, the system immediately detects the alignment error and can take corrective action, ensuring reliability while maintaining productivity
2Productivity
If all good die are picked and mounted without verification, then the manufacturing process is efficient, but alignment errors go undetected requiring costly retesting
Solution Approach 1:
Check GECs are preselected and marked for retention before processing begins. This preliminary action establishes a verification framework that enables continuous monitoring of alignment accuracy throughout the manufacturing process without interrupting the flow of picking and mounting good die
Solution Approach 2:
Check GECs serve as intermediary verification elements between the pick and place system and the final product quality. By leaving these specific GECs in place at predetermined locations, the system creates intermediate checkpoints that verify alignment accuracy without requiring verification of every single die placement
3Reliability
If check GECs are preselected using a specific algorithm, then pick error detection reliability is enhanced, but the process complexity increases
Solution Approach 1:
The system changes the parameter of check GEC selection from random or manual to algorithmically predetermined. This algorithm selects check GECs based on optimal distribution patterns that maximize error detection capability while minimizing the number of check GECs required, thereby enhancing reliability without proportionally increasing complexity
Data Source
AI summary
Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.