Die Attach Material Solidus Temperature Gradient for Flip-Chip Stress
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Solution Overview
Problem
Semiconductor packages with ultra-low K dielectrics and lead-free bumps experience inter-layer dielectric delamination under C4 flip-chip solder bumps, commonly known as white bumps or ghost bumps, particularly at the outer edges due to stress during the reflow cool-down process.
Innovation Solution
The use of electrically conductive die attach material with a higher solidus temperature on the inner section of the package substrate compared to the outer sections, allowing the inner material to solidify before the outer material during the cool-down process, thereby reducing stress on the die and adjacent ILD layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform die attach material is used across the entire package substrate, then manufacturing process is simple, but thermal expansion mismatch stress causes delamination at outer edges during cool-down
Solution Approach 1:
The patent applies different die attach materials with different solidus temperatures to different regions of the package substrate. Inner section contacts use material with higher solidus temperature while outer section contacts use material with lower solidus temperature, creating local quality variations that reduce thermal stress and prevent delamination during cool-down
2Reliability
If die attach material with higher solidus temperature is used, then stress during cool-down is reduced, but manufacturing complexity increases due to multiple material zones
Solution Approach 1:
The patent segments the die attach material into distinct zones based on their solidus temperatures. Inner section contacts use material with higher solidus temperature and outer section contacts use material with lower solidus temperature, allowing controlled solidification sequence that reduces thermal stress while maintaining manufacturability
3Area of stationary object
If outer row bumps are used, then package area is maximized, but delamination probability increases due to highest stress concentration
Solution Approach 1:
The patent applies different die attach materials to different regions: inner section contacts use material with higher solidus temperature while outer section contacts use material with lower solidus temperature. This local differentiation protects the high-stress outer row bumps by allowing them to solidify after inner sections, reducing stress concentration and delamination risk
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or eliminates white bumps by minimizing thermal expansion mismatch stress, improving the reliability of flip chip packages by maintaining the integrity of the inter-layer dielectric layers.
Implementation Method 1
the first solder compound is configured to become completely molten when heated and to solidify at a higher temperature during cool down than the second solder compound
Implementation Method 2
reducing the stress transferred to the die and specifically the ILD layers adjacent to the C4 bumps in the outer rows
Data Source
AI summary
A first set of electrically conductive cladding is disposed on an inner section of one external side of a package substrate. The first set electrically conductive cladding is fabricated with a first solder compound. A second set of electrically conductive cladding is disposed on an outer section of the one external side of the substrate. The second set of electrically conductive cladding consists of a second solder compound. The outer section can be farther away from a center of the one external side of the substrate than the inner section. During a reflow process, the first and second solder compounds are configured to become completely molten when heated and the first solder compound solidifies at a higher temperature during cool down than the second solder compound.