Die Backside Metallization and Surface Activated Bonding for Stacked Packages

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Solution Overview

Problem

Current computer systems with stacked die technology face signal propagation delays and thermal stress due to long interlinks between dies, which hinder communication speed and efficiency.

Innovation Solution

The implementation of die backside metallization (DBM) and surface activated bonding (SAB) for stacked die packages, which provide shorter interconnects and efficient data/power signal transfer, utilizing copper traces and atomically clean surface bonding to reduce thermal stress and enhance I/O capabilities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If direct silicon via technology is used for stacked die interlink, then interlink length is reduced, but thermal stress increases on the power-carrying die

Engineering Contradiction:
Improveinterlink lengthVSAvoidthermal stress
Core Design Contradiction:
Length of moving objectVSStress or pressure

Solution Approach 1:

The patent transitions from planar interlink routing to three-dimensional stacked die architecture, where dies are vertically stacked and interconnected through silicon vias. This dimensional change reduces interlink length by eliminating substrate-level routing, directly addressing the contradiction by achieving shorter interlinks while managing thermal stress through the vertical stacking configuration

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent modifies the electrical connection parameters by implementing DBM with copper traces and SAB bonding, changing the interlink characteristics from long substrate traces to short vertical vias. This parameter change reduces both interlink length and associated thermal stress by fundamentally altering the connection geometry and material properties

Inventive Principle:
Principle #35Parameter changes

2Length of moving object

If one die carries power source for another die in stacked configuration, then interlink length is reduced, but thermal stress is generated on the power-carrying die

Engineering Contradiction:
Improveinterlink lengthVSAvoidthermal stress
Core Design Contradiction:
Length of moving objectVSTemperature

Solution Approach 1:

The patent applies different material properties and structural characteristics to different regions of the stacked die system. Specifically, DBM with copper traces provides low-resistance power distribution on the backside, while SAB bonding creates strong thermal and electrical interfaces. This local differentiation allows power-carrying regions to be optimized for electrical performance while managing thermal stress through material selection and structural design

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent employs composite material structures including copper traces on silicon substrates, combined with SAB bonding interfaces. This composite approach creates a multi-material system where each material contributes specific properties: copper for electrical conductivity, silicon for structural integrity, and SAB bonding for strong thermal and electrical coupling, thereby managing thermal stress while enabling short interlinks

Inventive Principle:
Principle #40Composite materials

3Speed

If stacked die technology is used, then communication speed between dies is improved, but signal propagation delay and thermal issues arise from long interlinks

Engineering Contradiction:
Improvecommunication speedVSAvoidsignal propagation delay
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent achieves high communication speed by transitioning to vertical three-dimensional interconnection through silicon vias, eliminating long substrate-level traces. This dimensional change reduces signal propagation delay by shortening the physical path length while maintaining stacked die architecture for fast die-to-die communication

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the interlink parameters from long substrate traces to short vertical vias with DBM copper traces, fundamentally altering the signal path characteristics. This parameter change reduces signal propagation delay and improves communication speed by optimizing the electrical connection geometry and material properties

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves communication speed, reduces thermal mismatch, and minimizes vertical paths, allowing for higher signal transmission frequencies, reduced thermal stress, and lower fabrication costs, while enabling direct and efficient die-to-die communication.

Implementation Method 1

surface activated bonding (SAB) for stacked die packages

Methodology Applied
Scientific EffectSurface activated bonding:

Implementation Method 2

die backside metallization (DBM) and surface activated bonding (SAB) for stacked die packages

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS8110930B2Die backside metallization and surface activated bonding for stacked die packages
Publication Date: 2012.02.07 TAHOE RES LTD
  • US8110930B2 patent drawing
  • US8110930B2 patent drawing
  • US8110930B2 patent drawing

AI summary

Methods and apparatus to provide die backside metallization and/or surface activated bonding for stacked die packages are described. In one embodiment, an active metal layer of a first die may be coupled to an active metal layer of a second die through silicon vias and/or a die backside metallization layer of the second die. Other embodiments are also described.