Die Backside Profile for Residue Control and Edge Stress Relief

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Solution Overview

Problem

As inter-die spacing in semiconductor devices decreases, the risk of trapped residue increases, causing challenges and risks in downstream processes, such as oxide deposition and planarization.

Innovation Solution

A backside profile is formed on the semiconductor device with die-to-wafer bonding, including corner features and tapered sidewalls, which reduces the occurrence of trapped residue and relieves stress along die edges.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If inter-die spacing is decreased to improve device integration, then productivity and device density are improved, but the risk of trapped residue increases causing defects in downstream processes

Engineering Contradiction:
Improvedevice densityVSAvoidtrapped residue
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The backside profile is formed on the dies before die-to-wafer bonding occurs. This preliminary structuring of the die backside surfaces creates features that prevent residue accumulation in advance, addressing the trapped residue problem before it can affect downstream processes like oxide deposition and planarization

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The backside profile introduces localized structural variations on the die backside surfaces, creating specific geometric features (such as tapered walls and corner features) that have different properties from the flat original surfaces. These local structural changes specifically target residue accumulation zones without affecting the overall die geometry or bonding interface

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If inter-die spacing is decreased to improve device integration, then manufacturing precision is improved, but stress and cracks in insulation layers increase

Engineering Contradiction:
Improveinter-die spacing controlVSAvoidinsulation layer integrity
Core Design Contradiction:
Manufacturing precisionVSStrength

Solution Approach 1:

The backside profile is created before bonding to preemptively manage stress distribution. By structuring the die backside surfaces in advance, the design anticipates and mitigates stress concentration issues that would otherwise lead to insulation layer cracking during subsequent processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The backside profile creates localized structural features on the die backside that specifically address stress concentration at critical locations. These local modifications distribute mechanical stress more evenly across the insulation layers without compromising the precision of inter-die spacing

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250062129A1DIE BACKSIDE PROFILE for SEMICONDUCTOR DEVICES
Publication Date: 2025.02.20 APPLIED MATERIALS INC
  • US20250062129A1 patent drawing
  • US20250062129A1 patent drawing
  • US20250062129A1 patent drawing

AI summary

Embodiments of the disclosure include an apparatus and method of forming a backside profile in a semiconductor device that includes die-to-wafer bonding. The method generally includes removing a portion of a substrate layer included in a plurality of dies, the plurality of dies arranged on and bonded to an insulation layer included in a support structure, where the plurality of dies define a plurality of channels between adjacent dies, and forming a corner feature on a plurality of corners of the substrate layer adjacent to the plurality of channels. The use of a backside profile as described herein may mitigate the downstream process risks associated with trapped residue in the channels, and provide stress relief to the semiconductor device.