Die-Based Error Recovery Queues for NAND Memory Latency
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Solution Overview
Problem
Conventional memory controller processors face inefficiencies in scheduling error recovery commands, leading to increased latency due to the grouping of error recovery commands into a single queue, which does not account for different types and priorities of read commands, and worsens with wear and age of memory devices.
Innovation Solution
Implementing die-based error recovery message queues, where each NAND memory die has a separate queue for error recovery messages, allowing for parallel scheduling and prioritization of error recovery commands based on the destination die and type of read command.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If error recovery commands are grouped into a single queue, then the queue management is simple, but the latency of read commands increases significantly
Solution Approach 1:
The patent divides the single error recovery queue into multiple die-based queues, with each queue dedicated to a specific memory die. This segmentation allows parallel processing of error recovery commands across different dies, reducing the overall latency while maintaining manageable complexity through organized structure.
Solution Approach 2:
The patent introduces a new dimension of organization by mapping error recovery queues to specific memory dies spatially. Instead of a single sequential queue, the system creates a multi-dimensional queue structure where each die has its own dedicated queue, enabling parallel error recovery operations across multiple dies simultaneously.
2Device complexity
If a single error recovery queue is used, then the scheduling is simple, but the productivity of error recovery operations decreases
Solution Approach 1:
The patent segments the error recovery operations into die-specific queues, allowing multiple error recovery commands to be processed in parallel across different dies. This increases throughput by eliminating the serial bottleneck of a single queue while maintaining scheduling simplicity through die-based organization.
Solution Approach 2:
The patent ensures continuous error recovery processing by maintaining dedicated queues for each die, allowing the scheduler to continuously draw commands from multiple queues in parallel. This eliminates idle time and maintains continuous productive action across all memory dies.
3Device complexity
If all read commands are treated equally in the queue, then the queue structure is simple, but the priority handling of different command types is poor
Solution Approach 1:
The patent segments the queue system into die-based queues that can independently handle different command types and priorities. Each die queue can be managed separately, allowing the system to adapt to different command priorities without complicating the overall structure, as each queue remains simple but collectively they provide sophisticated priority handling.
Data Source
AI summary
A processor coupled to a NAND memory device comprising an n by m array of dies having n channels performs error recovery message scheduling and read error recovery on the dies by receiving indications of read errors responsive to attempted execution of a read command on a destination die and creates an error recovery message or instruction in response to the indication. The processor determines the destination die of the error recovery message and sends the error recovery message to a die queue based on the determined destination die. The n×m die queues can each be further divided into p priority queues, and error recovery messages are sent to the appropriate die priority queue based on a priority associated with the error recovery message. The processor fetches error recovery messages from a head of each die priority queue and performs read error recovery at the destination die.