Die-Based Trimming for Non-Volatile Memory Yield

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Solution Overview

Problem

Current non-volatile memory fabrication methods face challenges in accurately programming memory cells due to fabrication tolerances, leading to inadequate yields and performance, particularly in battery-powered devices where low operating voltage is desirable to reduce power consumption and extend device lifetime.

Innovation Solution

Implementing an on-chip state machine for parallel programming of memory pages, allowing for die-by-die trimming of memory devices by determining and adjusting programming parameters such as voltage and pulse width to match individual die performance, thereby improving yield and reducing testing time and costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer-based trimming is used to program memory cells, then the entire wafer can be adjusted to meet design specifications, but adequate yields and performance of individual memory dies cannot be achieved

Engineering Contradiction:
ImproveyieldVSAvoidprogramming accuracy
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The invention transitions from wafer-based trimming to die-based trimming, segmenting the trimming process into individual die level. Each die is independently tested and trimmed based on its specific performance characteristics, allowing precise programming adjustments for each die while maintaining overall yield improvement.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention implements local quality by tailoring trimming parameters to each individual die's performance characteristics. Instead of applying uniform trimming across the entire wafer, each die receives customized trimming based on its measured programming time and performance, ensuring optimal programming accuracy for each specific die.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If standard programming parameters are used for all dies, then the fabrication process is simple, but fabrication tolerances cause varying performance that prevents adequate programming accuracy

Engineering Contradiction:
Improveprogramming accuracyVSAvoidtrimming process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The invention performs preliminary testing of each die to measure its actual programming time and performance characteristics before applying trimming. This preliminary action enables data-driven trimming decisions, where the measured performance of each die is used to determine the appropriate trimming parameters, achieving high programming accuracy while managing complexity through systematic measurement and adjustment.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If die-by-die trimming is implemented to improve yield and performance, then individual die performance can be optimized, but testing time and fabrication complexity increase

Engineering Contradiction:
ImproveyieldVSAvoidtesting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The invention implements feedback by measuring the actual programming time of each die and using this information to determine the appropriate trimming parameters. The measured performance data feeds back into the trimming process, allowing iterative adjustment and optimization of programming parameters for each die, which improves yield while managing testing time through efficient feedback-driven adjustments.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS7512507B2Die based trimming
Publication Date: 2009.03.31 MICRON TECHNOLOGY INC
  • US7512507B2 patent drawing
  • US7512507B2 patent drawing
  • US7512507B2 patent drawing

AI summary

Methods and structures are described to provide trims for die on a wafer. The trims are set on a die-by-die basis instead of a wafer basis. Accordingly, the individual die are more finely tuned and more die operate at the target specifications so that yield is increased. In an embodiment, the odd and even blocks of each non volatile memory die are erased and then programmed to test the program time. Statistical analysis of the tested program times is performed. Based on this analysis the trim values are determined and programmed into the die. Accordingly, each die on a wafer has its individual trim settings.