Die-to-Die Bonding with Carrier Wafers for Uniform 3D Memory Stacking
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Solution Overview
Problem
Conventional bonding methods for stacking semiconductor devices, such as chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding, face challenges like space wastage, reduced throughput, and lower yields due to non-uniform die distribution and uncertainty in fabrication processes.
Innovation Solution
The method involves dicing device wafers to obtain functional dies, which are then placed on carrier wafers with precision alignment and bonding, using hybrid bonding techniques to form semiconductor devices with uniform die distribution and full coverage, thereby increasing yield and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional bonding methods (chip-to-chip, chip-to-wafer, wafer-to-wafer) are used for stacking semiconductor devices, then bonding can be achieved, but space is wasted, throughput is reduced, and yields are lowered due to non-uniform die distribution and fabrication uncertainty
Solution Approach 1:
The patent applies preliminary action by pre-attaching dies to carrier wafers in a controlled manner before the bonding process. Dies are placed on carrier wafers with predetermined positions and orientations, ensuring uniform distribution prior to bonding. This pre-arrangement eliminates the uncertainty and non-uniformity that would otherwise occur during the bonding process itself, thereby improving both throughput and manufacturing precision.
Solution Approach 2:
The patent introduces carrier wafers as intermediary elements between the dies to be bonded. These carrier wafers serve as temporary substrates that hold the dies in precise positions during handling and alignment. The carrier wafers mediate the bonding process by providing a stable platform that ensures uniform die distribution and facilitates precise alignment, thereby resolving the contradiction between productivity and manufacturing precision.
2Reliability
If conventional bonding methods are used, then bonding can be performed, but yields are reduced due to non-uniform die distribution and fabrication uncertainty
Solution Approach 1:
The patent performs preliminary alignment and attachment of dies to carrier wafers before the actual bonding process. Dies are positioned with precise orientation and location on the carrier wafers in advance, ensuring that when bonding occurs, the alignment is already optimized. This preliminary action eliminates fabrication uncertainty and ensures high bonding yield by preventing misalignment defects.
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with a more precise positioning system. Instead of relying on mechanical fixtures and manual alignment during bonding, the dies are pre-positioned on carrier wafers using precise placement mechanisms that ensure sub-micron accuracy. This substitution of the alignment mechanism dramatically improves both yield and precision.
Data Source
AI summary
Embodiments of die-to-die bonding schemes of three-dimensional (3D) memory devices are provided. In an example, a method for bonding includes dicing one or more device wafers to obtain a plurality of dies, placing at least one first die of the plurality of dies onto a first carrier wafer and at least one second die of the plurality of dies onto a second carrier wafer, and bonding the at least one first die each with a respective second die. The at least one first die and the at least one second die each are functional. In some embodiments, the method also includes removing, respectively, the first carrier wafer and the second carrier wafer to form a plurality of bonded semiconductor devices each having one of the first dies and the respective second die.