Semiconductor Die Bonding With Encapsulated Support for Size Mismatch
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Solution Overview
Problem
The integration of semiconductor dies with different design considerations, such as logic and memory functions, often results in physical and structural mismatches that cause issues during bonding, leading to potential defects and stress-related problems.
Innovation Solution
The solution involves bonding smaller semiconductor dies with larger ones on a wafer, using an encapsulant to provide structural support and protection, and employing techniques like through-silicon vias (TSVs) and redistribution layers to facilitate electrical connections while managing size mismatches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor dies with different design considerations (logic and memory functions) are designed and manufactured separately, then design flexibility and manufacturing efficiency are improved, but physical and structural mismatches occur that cause bonding problems
Solution Approach 1:
The patent introduces an intermediary carrier substrate that receives both logic and memory dies during assembly. This carrier acts as a mediator that accommodates the different sizes and structures of separately manufactured dies, enabling precise alignment and bonding without requiring the dies themselves to be perfectly matched. The carrier substrate provides reference marks and structural features that facilitate accurate positioning of dies with different design considerations.
2Adaptability or versatility
If smaller semiconductor dies are bonded to larger semiconductor dies, then functional integration is improved, but structural integrity and stress distribution deteriorate
Solution Approach 1:
The patent applies local quality by providing enhanced structural support specifically at the bonding interfaces between dies of different sizes. The carrier substrate includes localized reinforcement features, such as thicker substrate regions or additional anchoring structures, positioned at critical bonding areas. This localized enhancement strengthens the joint between smaller and larger dies without requiring the entire structure to be uniformly reinforced, thereby maintaining functional integration while improving structural integrity.
3Reliability
If through-silicon vias and redistribution layers are used to facilitate electrical connections, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming through-silicon vias and redistribution layers on the carrier substrate before bonding the semiconductor dies. This advance preparation ensures that electrical connection paths are already established and aligned with the bonding interfaces. By pre-forming these conductive structures on the carrier, the patent simplifies the overall manufacturing process compared to forming them after die bonding, as the carrier provides a stable platform for precise via formation and alignment.
Data Source
AI summary
A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.