Integrated Die-to-Die Bridge Layout for Low-Inductance Power Delivery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor package layouts face power integrity challenges due to undesired AC loop inductance and impedance load-line performance issues, particularly in multi-chip packages with embedded bridge components that require high-density coupling between multiple dies, leading to increased power supply noise and discontinuities in reference planes.
Innovation Solution
The integration of a bridge component with a middle power-ground section in semiconductor packages, which includes embedded capacitors and conductive traces to isolate and connect power and ground networks between dies, reducing AC loop inductance and improving impedance load-line performance by maintaining continuous power-ground connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional components are embedded under a centrally located semiconductor die, then device functionality is improved, but power line continuity is interrupted and power integrity deteriorates
Solution Approach 1:
The package structure is segmented into multiple layers with power lines routed through different levels. Power lines are divided into first power lines connecting to first semiconductor components and second power lines connecting to second semiconductor components, allowing embedding of components without interrupting the entire power distribution network.
Solution Approach 2:
Power lines are transitioned from a two-dimensional planar layout to a three-dimensional multi-layer configuration. The power distribution network utilizes vertical stacking and lateral routing across multiple package layers, enabling power delivery around embedded components rather than being blocked by them.
2Productivity
If high-density coupling is implemented between multiple dies, then interconnect density is improved, but AC loop inductance increases and power integrity deteriorates
Solution Approach 1:
Different regions of the package are assigned different functions: first package layers are dedicated to power distribution with large-area power lines for low inductance, while second package layers are dedicated to signal interconnects for high-density coupling. This spatial separation of power and signal paths optimizes each function independently.
Solution Approach 2:
A third semiconductor component is introduced as an intermediary element positioned between the first and second semiconductor components. This intermediate component facilitates power and signal distribution while maintaining controlled impedance and reducing loop inductance through its strategic placement and coupling characteristics.
3Power
If power lines are routed through package layers, then power distribution is improved, but reference plane discontinuities occur and impedance performance deteriorates
Solution Approach 1:
Reference planes are pre-configured in each package layer before component assembly and interconnect formation. The reference planes are established as continuous conductive structures that extend across package layers, with via connections and trace routing designed in advance to maintain impedance control and prevent discontinuities.
Solution Approach 2:
Power lines and reference planes are merged into integrated power distribution structures that span multiple package layers. The power lines are coupled to reference planes through via connections and lateral traces, creating unified power-delivery pathways that maintain continuous reference planes while distributing power to multiple semiconductor components.
Data Source
AI summary
An electronic device and associated methods are disclosed. In one example, the electronic device can include a semiconductor package including a package substrate, a first semiconductor die on the package substrate, a second semiconductor die on the package substrate, a third semiconductor die on the package substrate, and a bridge interconnect at least partially embedded in the package substrate. The bridge interconnect can include a first bridge section coupling the first semiconductor die to the second semiconductor die, a second bridge section coupling the second semiconductor die to the third semiconductor die, and a power-ground section between the first section and the second section, the power-ground section comprising first and second conductive traces coupled to the second semiconductor die.