Die Structure Buffer Layers for CTE Mismatch Stress Relief
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing stress on bonding interfaces of integrated circuit dies due to coefficient of thermal expansion (CTE) mismatch between encapsulants and dies, leading to potential delamination and reliability issues during high-temperature expansion.
Innovation Solution
Incorporating a stress reduction compound as buffer layers around integrated circuit dies, which have a CTE greater than the dies but less than the encapsulant, to mitigate stress and improve bonding interface reliability, along with a liner layer for protection and a molding compound with a higher CTE for encapsulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulant with high CTE is used for encapsulation, then encapsulation effectiveness is improved, but stress on bonding interface increases
Solution Approach 1:
A buffer layer is introduced as an intermediary component between the die and the encapsulant. This buffer layer has a CTE that is higher than the die but lower than the encapsulant, serving as a stress-absorbing intermediary that prevents direct transmission of thermal expansion stress from the high-CTE encapsulant to the bonding interface, thereby maintaining encapsulation effectiveness while reducing stress on the die-encapsulant interface
2Stress or pressure
If buffer layer with intermediate CTE is added, then stress on bonding interface is reduced, but device structure becomes more complex
Solution Approach 1:
The encapsulation structure is segmented into distinct functional layers: the die, the buffer layer with intermediate CTE properties, and the encapsulant. This segmentation allows each layer to be independently optimized for its specific function - the buffer layer specifically for stress management - while maintaining overall structural integrity and simplifying the design process through clear functional division
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer layers effectively reduce stress on bonding interfaces by 32%, enhancing the yield and reliability of die structures by managing thermal expansion mismatch and preventing delamination.
Implementation Method 1
coefficient of thermal expansion (CTE) mismatch between encapsulants and dies, leading to potential delamination and reliability issues during high-temperature expansion
Data Source
AI summary
Various embodiments include die structures and methods of forming die structures. In an embodiment, a device includes: a lower substrate; upper integrated circuit dies bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds, the upper integrated circuit dies including a semiconductor material; a buffer layer around the upper integrated circuit dies, the buffer layer including a stress reduction compound, a coefficient of thermal expansion of the stress reduction compound being greater than a coefficient of thermal expansion of the semiconductor material; and an encapsulant around the buffer layer and the upper integrated circuit dies, the encapsulant including a molding compound, a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound.