Semiconductor Die Bump Bases for Tin Wicking and Warpage Control

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Solution Overview

Problem

The existing technologies face challenges in reducing defects in interconnects between semiconductor dies and package substrates, particularly due to issues like tin shifting, wicking, and warpage, which are exacerbated by the miniaturization of bumps and increased aspect ratios.

Innovation Solution

The proposed solution involves fabricating dummy bumps adjacent to operational bridge bumps to prevent tin shifting, using non-circular bumps such as hexagonal shapes to reduce wicking, and varying the heights of bumps spatially to compensate for warpage, thereby enhancing the reliability and efficiency of interconnects.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the size of bumps and pads is decreased to meet miniaturization requirements, then the size of integrated circuits and packages is reduced, but the aspect ratio of bumps increases leading to tin shifting and wicking defects

Engineering Contradiction:
Improvebump sizeVSAvoidtin placement accuracy
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent modifies the geometric parameters of the bump base from circular to non-circular shapes (hexagonal, square, rectangular) to change the surface area distribution and reduce tin wicking. This parameter change allows maintaining smaller bump sizes while improving tin placement accuracy by preventing lateral flow during reflow processing.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent segments the bump structure into two distinct parts: a smaller top portion containing the tin and a larger base portion with non-circular geometry. This segmentation allows the top to remain small for miniaturization while the base provides sufficient support area to prevent tin shifting and wicking.

Inventive Principle:
Principle #1Segmentation

2Productivity

If the aspect ratio of bumps is increased to reduce pitch, then more interconnects can be packed, but tin wicking and shifting defects increase

Engineering Contradiction:
Improveinterconnect densityVSAvoidinterconnect defect rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By changing the base shape parameter from circular to non-circular (hexagonal, square, rectangular), the patent increases the effective base area without increasing the bump height, thereby reducing the aspect ratio while maintaining high interconnect density. This parameter change directly reduces tin wicking and shifting defects.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent addresses the aspect ratio problem by expanding in the lateral dimension through non-circular base shapes rather than increasing height. This dimensional approach allows higher interconnect density through better space utilization while maintaining lower aspect ratios for reliability.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If circular bump shapes are used, then fabrication is simple, but tin wicking occurs due to high surface area to volume ratio

Engineering Contradiction:
Improvebump fabrication simplicityVSAvoidtin wicking
Core Design Contradiction:
Ease of manufactureVSObject-generated harmful factors

Solution Approach 1:

The patent applies asymmetry by using non-circular (hexagonal, square, rectangular) base shapes instead of circular ones. This asymmetric geometry reduces the perimeter-to-area ratio, thereby reducing the surface area available for tin wicking while maintaining ease of fabrication through standard lithographic patterning processes.

Inventive Principle:
Principle #4Asymmetry

4Device complexity

If warpage is not compensated, then manufacturing process is simpler, but bump coplanarity deteriorates leading to attachment defects

Engineering Contradiction:
Improvemanufacturing process complexityVSAvoidbump coplanarity
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent applies local quality by varying the base dimensions of bumps in different locations on the substrate. Bumps in regions experiencing upward warpage have smaller bases, while bumps in regions experiencing downward warpage have larger bases. This localized adjustment compensates for warpage and maintains bump coplanarity without adding complex manufacturing steps.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12334422B2Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates
Publication Date: 2025.06.17 INTEL CORP
  • US12334422B2 patent drawing
  • US12334422B2 patent drawing
  • US12334422B2 patent drawing

AI summary

Methods and apparatus to reduce defects in interconnects between semiconductor dies and package substrates are disclosed. An apparatus includes a substrate and a semiconductor die mounted to the substrate. The apparatus further includes an array of bumps to electrically couple the die to the substrate. Each of the bumps have a corresponding base. Different ones of the bases have different widths that vary spatially across the array of bumps.