Semiconductor Die Bump Layout With Back-Side Power for Lower IR Drop
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Solution Overview
Problem
Existing integrated circuit (IC) devices face challenges in miniaturization and multi-functionality due to inadequate voltage drop management in high-density interconnects, particularly in arranging input/output (I/O) bumps on the limited peripheral edge of semiconductor dies.
Innovation Solution
The electronic device incorporates a semiconductor die with a first region near the peripheral edge featuring signal and power bumps on opposite surfaces, overlapping the first region, and a second region for central functional cells, utilizing back-side power technology to reduce front-side routing and improve IR drop by rearranging bump arrays to optimize signal and power routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If high density interconnects are used for signal routing and power delivery, then miniaturization and multi-functionality are improved, but voltage drop (IR drop) increases
Solution Approach 1:
The patent utilizes both front-side and back-side surfaces of the semiconductor die to arrange bump arrays, transitioning from a single-plane to a dual-plane configuration. This dimensional change allows power bumps to be positioned closer to functional cells through through-substrate vias, reducing current path length and IR drop while maintaining miniaturization benefits
2Quantity of substance
If bump arrays are arranged in multiple rows on the peripheral edge, then more I/O connections are achieved, but the number of rows increases complexity and IR drop
Solution Approach 1:
The patent segments the bump arrays into front-side bump arrays and back-side bump arrays, with different functional cells positioned on opposite surfaces. This segmentation allows each array to have fewer rows while collectively providing the required I/O connections, reducing the complexity associated with managing multiple rows on a single side
3Reliability
If more power bumps are allocated to first functional cells, then their performance is improved, but fewer power bumps remain for second functional cells
Solution Approach 1:
By utilizing the back-side surface for additional power bumps and implementing through-substrate via connections, the patent effectively doubles the available power delivery paths to first functional cells. This dimensional approach satisfies the power requirements of first functional cells while maintaining adequate power bump allocation for second functional cells through the shared substrate infrastructure
Data Source
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AI summary
An electronic device is provided. The electronic device includes a semiconductor die. The semiconductor die has a first region of a first functional cell close to the peripheral edge of the semiconductor die. The semiconductor die includes a semiconductor substrate, a first signal bump, and a first power bump. The first signal bump and the first power bump are disposed on opposite surfaces of the semiconductor substrate and electrically connected to the first functional cell. The first signal bump and the first power bump both overlap the first region.