Die Cavity Substrate Packaging for Low-Stress Semiconductor Assembly
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Solution Overview
Problem
The packaging of semiconductor devices using glob top dielectric material often experiences mechanical stress due to coefficient of thermal expansion (CTE) mismatch, leading to delamination and connection failures during thermal cycling, especially in devices like imagers, LEDs, and MEMS devices.
Innovation Solution
A semiconductor package with a die cavity substrate design that reduces the volume of dielectric material and mechanical stress by forming a die cavity in the package substrate, allowing the dielectric material to extend above the substrate surface, and optionally using a bond finger shelf to contain the material, thereby minimizing contact and stress between the dielectric and the semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric material is used to cover bond pads and conductors, then electrical connections are protected, but mechanical stress and delamination occur during thermal cycling due to CTE mismatch
Solution Approach 1:
The dielectric material coverage is segmented into two distinct regions: a first dielectric material covering the bond pads and conductors, and a second dielectric material covering the semiconductor die. This segmentation allows each dielectric region to be optimized independently for its specific function, reducing overall mechanical stress while maintaining connection integrity.
Solution Approach 2:
Different dielectric materials are applied to different locations based on their specific requirements. The first dielectric material is used where electrical protection is needed (bond pads and conductors), while the second dielectric material is used where mechanical stress reduction is critical (semiconductor die). This local quality approach ensures each area has the optimal material properties for its function.
2Reliability
If glob top dielectric material is used to cover the semiconductor die, then the die is protected, but the volume of dielectric material increases and mechanical stress increases
Solution Approach 1:
The dielectric coverage is divided into two segments: a first dielectric material for electrical protection of conductors and a second dielectric material for mechanical protection of the die. This segmentation eliminates the need for excessive dielectric material while maintaining adequate protection, thereby reducing the overall volume of dielectric material required.
Solution Approach 2:
The patent extracts the protective function from a single comprehensive dielectric layer and separates it into two specialized dielectric materials. This extraction allows each material to provide protection only where needed, eliminating redundant dielectric material volume while maintaining die protection.
3Reliability
If dielectric material covers the bond pads and conductors, then electrical connections are protected, but material costs increase due to excessive dielectric material volume
Solution Approach 1:
The dielectric material application is segmented into two distinct regions with different material properties and thicknesses. The first dielectric material covers only the necessary electrical connection areas (bond pads and conductors), while the second dielectric material covers the die area. This segmentation eliminates unnecessary dielectric material usage while maintaining electrical connection protection.
Solution Approach 2:
Different dielectric materials are applied locally to different areas based on their specific requirements. This local quality approach ensures dielectric material is used only where necessary for electrical protection, reducing overall material consumption and cost while maintaining connection reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces mechanical stress and delamination issues during thermal cycling, maintaining the integrity of electrical connections and reducing material costs by minimizing the volume of dielectric material needed, while ensuring compatibility with various thermal cycles.
Implementation Method 1
A dielectric material, such as mold compound, a dielectric material referred to as glob top mold compound, or another dielectric material, covers the electrical connections and the bond pads of the semiconductor device
Implementation Method 2
The packaging of semiconductor devices using glob top dielectric material often experiences mechanical stress due to coefficient of thermal expansion (CTE) mismatch
Data Source
AI summary
An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.


