Semiconductor Die Chamfers for Thermal Stress Relief in Packages

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Solution Overview

Problem

Semiconductor packages face challenges with thermal stress, particularly at specific locations due to the arrangement of semiconductor dies on the package substrate, leading to adhesive stress and potential delamination.

Innovation Solution

Incorporating stress-reduction structures, specifically chamfers at the corners of semiconductor dies, to mitigate thermal stress by altering the stress distribution and reducing the concentration of stress at critical points.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If semiconductor dies are arranged in three-dimensional stacked configurations to improve integration density, then integration density and bandwidth are improved, but thermal stress concentration and adhesive failure risk increase

Engineering Contradiction:
Improveintegration densityVSAvoidthermal stress
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by modifying only the corner regions of semiconductor dies with chamfers, while keeping the rest of the die structure intact. This localized modification reduces thermal stress concentration at corners without affecting the overall three-dimensional stacked configuration and integration density.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The chamfers are formed on the semiconductor dies before packaging and stacking. This preliminary action prevents thermal stress concentration from developing during subsequent thermal cycling, thereby preventing adhesive failure before it occurs.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If chamfers are formed at the corners of semiconductor dies to reduce thermal stress, then adhesive strength and reliability are improved, but manufacturing complexity increases

Engineering Contradiction:
Improveadhesive strengthVSAvoidmanufacturing process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The stress reduction feature is segmented to only affect the corner regions of the semiconductor dies, rather than modifying the entire die surface. This segmentation minimizes the impact on manufacturing while achieving the stress reduction goal at the critical locations.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If corner portions of semiconductor dies are removed to form chamfers, then stress concentration is reduced, but die volume and active area are decreased

Engineering Contradiction:
Improvestress concentrationVSAvoiddie volume
Core Design Contradiction:
Object-affected harmful factorsVSVolume of moving object

Solution Approach 1:

The chamfer modification is applied only to the corner portions of the semiconductor dies, preserving the majority of the die volume and active area. This localized approach reduces stress concentration while minimizing the loss of functional material.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The chamfers remove only the minimal necessary corner portions to achieve stress reduction, avoiding excessive material removal. This partial action is sufficient to mitigate stress concentration while preserving die volume.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20250105170A1Semiconductor package including stress-reduction chamfers and methods for forming the same
Publication Date: 2025.03.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250105170A1 patent drawing
  • US20250105170A1 patent drawing
  • US20250105170A1 patent drawing

AI summary

A semiconductor package includes: a package substrate including a horizontal top surface; an interposer bonded to the top surface of the package substrate; a semiconductor die bonded to a top surface of the interposer, the semiconductor die including a bottom surface that faces the top surface of the interposer, and chamfers formed in corners of the bottom surface of the semiconductor die; and a molding layer surrounding the semiconductor die and filling the chamfers.