Die Controller Logic for Burst Data Transfers
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Solution Overview
Problem
Current communication interfaces in die architectures, such as SPI, face inefficiencies in data transfer processes, particularly in burst data transfers, requiring multiple commands and address bytes, which can be optimized for faster and more efficient data exchange.
Innovation Solution
The implementation of controller logic that asserts a chip select signal to initiate and maintain data exchanges over communication buses, allowing for continuous data transfer without the need for additional commands or address bytes, by determining whether subsequent data requests are sequential based on stored addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional SPI communication protocol is used for data transfer, then communication reliability is maintained, but data transfer speed and efficiency deteriorate due to multiple commands and address bytes required for each transfer
Solution Approach 1:
The patent applies preliminary action by asserting the chip select signal in advance and maintaining it across multiple sequential data transfers. The controller logic determines a final address from the first data transfer request, asserts the chip select signal, and then continues to transfer additional data without de-asserting and re-asserting the signal, thereby eliminating redundant commands and address bytes.
Solution Approach 2:
The patent implements continuity of useful action by keeping the chip select signal asserted throughout a burst of sequential data transfers. The controller logic receives multiple data transfer requests and continues transferring data over the communication bus without interrupting the chip select signal, allowing continuous data exchange without the overhead of repeated command sequences.
2Productivity
If multiple commands and address bytes are sent for each data transfer, then address precision is maintained, but data transfer efficiency deteriorates
Solution Approach 1:
The patent applies merging by combining multiple data transfer operations into a single continuous transaction. The controller logic merges the chip select signal assertion across multiple data transfers, eliminating the need for separate command and address sequences for each transfer, thereby reducing the time required for burst data transfers.
3Ease of operation
If chip select signal is de-asserted and re-asserted for each data transfer, then device control precision is maintained, but communication overhead increases
Solution Approach 1:
The controller logic performs preliminary action by determining the final address from the first data transfer request and asserting the chip select signal accordingly. This preliminary determination allows the system to maintain control precision while avoiding the overhead of repeated address transmission for subsequent sequential transfers.
Data Source
AI summary
Methods and apparatuses directed to more efficient data transfers within die architectures. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic can receive an initial data transfer request over the first communication bus, and determine a final address of the initial data transfer request. Further, the controller logic can assert a chip select signal of the second communication bus to initiate a data exchange. While asserting the chip select signal, the controller logic can receive an additional data transfer request over the first communication bus, and determine an initial address of the additional data transfer request. Based on the determined initial and final addresses, the controller logic can initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.