Die Extension Region Vias for Semiconductor Interconnect
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Solution Overview
Problem
The existing methods for interconnecting stacked semiconductor die often result in damage to the wafer and die due to drilling through hole vias in the active area or saw streets during the manufacturing process.
Innovation Solution
A method involving the formation of a die extension region with a polymer or insulating material around the periphery of the semiconductor die, where conductive vias are created through this region, allowing for electrical connectivity without drilling through the active area, and subsequent singulation to separate the die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through hole vias are drilled in the active area of the die or in saw streets on the wafer, then electrical interconnection between stacked semiconductor die is achieved, but damage to the wafer and die occurs
Solution Approach 1:
A die extension region made of polymer material is introduced as an intermediary structure between the active die area and the through hole vias. This extension region allows vias to be formed outside the active area while still providing electrical interconnection functionality, thus mediating between the need for connectivity and the need to avoid damage to active components
Solution Approach 2:
The solution moves the via formation location from the traditional two-dimensional plane of the active die area to a three-dimensional extension region that protrudes from the die periphery. This dimensional change allows vias to be positioned away from sensitive active areas while maintaining electrical connectivity function
2Productivity
If smaller, higher-density integrated circuits are produced, then device integration is improved, but signal propagation and capacitance increase
Solution Approach 1:
By forming vias through the die extension region that protrudes from the die periphery, the electrical interconnection path is optimized in three-dimensional space. This allows for shorter and more direct signal paths compared to traditional planar routing, reducing signal propagation delay and capacitance effects while enabling higher device integration density
Data Source
AI summary
A semiconductor wafer contains a plurality of semiconductor die. The semiconductor wafer is diced to separate the semiconductor die. The semiconductor die are transferred onto a carrier. A die extension region is formed around a periphery of the semiconductor die on the carrier. The carrier is removed. A plurality of through hole vias (THV) is formed in first and second offset rows in the die extension region. A conductive material is deposited in the THVs. A first RDL is formed between contact pads on the semiconductor die and the THVs. A second RDL is formed on a backside of the semiconductor die in electrical contact with the THVs. An under bump metallization is formed in electrical contact with the second RDL. Solder bumps are formed on the under bump metallization. The die extension region is singulated to separate the semiconductor die.