Die Group Voltage Offset Bin Selection for Memory Devices

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Solution Overview

Problem

Existing memory sub-systems face increased bit error rates due to temporal voltage shift caused by slow charge loss in memory cells, which current strategies fail to adequately address, resulting in inefficiencies and high error rates.

Innovation Solution

The implementation of a memory sub-system that selectively tracks temporal voltage shift for programmed blocks grouped by die groups, applying appropriate voltage offsets based on block affiliation to improve read operations, using a die-group-based error avoidance strategy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If voltage offset bin selection is performed for each individual die, then measurement precision is improved, but device complexity increases

Engineering Contradiction:
Improvevoltage offset measurement precisionVSAvoidcalibration and metadata management complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent combines multiple dice into die groups that share common voltage offset bin characteristics. Instead of calibrating and tracking each die individually, the system performs calibration at the die group level and applies the same voltage offset bin selection to all dice within a group. This merging approach maintains measurement precision for voltage offset compensation while significantly reducing the complexity of calibration operations and metadata management.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates die groups that serve as universal units for voltage offset management. Each die group is assigned a single voltage offset bin that applies universally to all dice within that group. This universal approach allows the system to handle voltage variations across multiple dice using a unified calibration and selection mechanism, reducing the need for individual die-specific calibration while maintaining adequate precision for error reduction.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If individual die calibration is performed, then bit error rate is reduced, but productivity decreases

Engineering Contradiction:
Improvebit error rateVSAvoidcalibration speed and operational efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges calibration operations across multiple dice by grouping them into die groups with similar voltage characteristics. The calibration process is performed once per die group rather than individually for each die, significantly accelerating calibration speed and improving productivity. This merged approach maintains adequate bit error rate reduction by ensuring that dice within the same group receive appropriate voltage offset compensation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary calibration at the die group level before actual memory operations. By pre-determining the voltage offset bin for each die group and storing this information in metadata, the system eliminates the need for repeated individual die calibration during operation. This preliminary action at the group level improves productivity while maintaining the reliability benefits of voltage offset compensation.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If voltage offset tracking is implemented for all dice, then bit error rate improves, but loss of information increases

Engineering Contradiction:
Improvebit error rateVSAvoidmetadata storage requirements
Core Design Contradiction:
ReliabilityVSLoss of information

Solution Approach 1:

The patent merges voltage offset tracking information by storing a single voltage offset bin value for each die group rather than individual values for each die. This consolidation significantly reduces metadata storage requirements while maintaining the bit error rate improvement benefits. The merged tracking approach captures the essential voltage characteristics needed for error reduction without the overhead of individual die-specific metadata.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent extracts only the essential voltage offset bin information at the die group level, rather than storing complete individual die calibration data. By taking out only the necessary voltage offset bin assignment for each die group, the system achieves bit error rate improvement while minimizing metadata storage requirements. This extraction approach focuses on storing only the critical information needed for voltage compensation during read operations.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11837291B2Voltage offset bin selection by die group for memory devices
Publication Date: 2023.12.05 MICRON TECHNOLOGY INC
  • US11837291B2 patent drawing
  • US11837291B2 patent drawing
  • US11837291B2 patent drawing

AI summary

One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.