Die-in-Die Cavity Packaging for Secure ASIC Customization
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Solution Overview
Problem
Government policies require the use of 'trusted foundries' for sensitive microelectronics, limiting customization of ASICs with modern technologies due to supply and capability constraints, such as lack of non-volatile memory and limited analog-digital converters.
Innovation Solution
A system-in-package (SIP) with die-in-die cavity packaging, where a primary ASIC die has a cavity integrated into its active side, encapsulating a secondary die like non-volatile memory or ADC, connected via additive redistribution layers, enabling post-foundry enhancement while preserving security and integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If trusted foundries are used for ASIC production, then security and integrity are ensured, but customization capability with modern technologies is limited
Solution Approach 1:
The system divides the ASIC functionality into two separate dies: a primary die produced at a trusted foundry for security-critical functions, and a secondary die produced at a mainstream foundry for customizable functions. This segmentation allows each die to be manufactured with appropriate security measures while enabling broader customization options.
Solution Approach 2:
The secondary die is physically encapsulated within a cavity on the primary die, creating a die-in-die cavity packaging structure. This nesting approach integrates the customizable secondary die with the secure primary die into a single unified package, maintaining security while adding functionality.
2Reliability
If trusted foundries are used for ASIC production, then device security is protected, but access to advanced technologies is restricted
Solution Approach 1:
The system separates security-critical ASIC functions from advanced technology functions into different dies. The primary die contains security-critical code produced at a trusted foundry, while the secondary die incorporates advanced technologies like non-volatile memory or high-performance ADCs from mainstream foundries.
Solution Approach 2:
The primary die acts as an intermediary that interfaces between the secure trusted foundry environment and the advanced mainstream foundry technologies. It provides controlled access to the secondary die while maintaining security boundaries.
3Adaptability or versatility
If die-in-die cavity packaging is used, then customization with advanced technologies is enabled, but manufacturing complexity increases
Solution Approach 1:
The cavity is pre-formed on the primary die before the secondary die is attached. This preliminary action simplifies the overall manufacturing process by preparing the integration interface in advance, allowing for more straightforward assembly of the die-in-die structure.
Solution Approach 2:
The patent employs additive redistribution layers (RDL) to create electrical interconnections between the primary and secondary dies. This copying approach allows flexible routing of signals without requiring complex direct bonding, simplifying the interconnection process.
4Adaptability or versatility
If die-in-die cavity packaging is used, then functionality and customization are enhanced, but manufacturing process difficulty increases
Solution Approach 1:
The cavity formation and preparation steps are performed on the primary die before secondary die attachment. This preliminary preparation includes creating the cavity, applying underfill material, and positioning reference marks, which simplifies the subsequent assembly process.
Solution Approach 2:
Additive redistribution layers are used to replicate and extend electrical connections between dies. This copying method allows for flexible signal routing and impedance matching without requiring precise direct bonding, reducing manufacturing difficulty.
Data Source
AI summary
A system-in-package (SIP) incorporating die-in-die cavity packaging may include hybrid dies fabricated by milling or otherwise creating a cavity through the additive surfaces of a primary application specific integrated circuit (ASIC) die configured for flip-chip bonding and encapsulating a secondary die such as a Flash/non-volatile memory module, analog-digital converter (ADC), or other processing circuit into the cavity. The primary and secondary dies are then connected by the addition of redistribution layers. The resulting hybrid die may then be vertically integrated into the SIP along with additional memory modules or dies.