Die Interconnect Link Bandwidth Management via Error Lane Segmentation
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Solution Overview
Problem
Die-to-die interconnect architectures face issues with reduced data throughput and reliability due to data lane errors, often caused by thermal conditions, leading to inefficient renegotiation processes that decrease the number of active data lanes.
Innovation Solution
Implementing an error status register and processor to identify error-free data lanes, determine a link width based on these lanes, and initiate a renegotiation process to establish a data link with a higher bandwidth using error-free lanes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the negotiation process reduces the number of data lanes in response to errors, then reliability is improved, but data throughput decreases
Solution Approach 1:
The patent segments the data link into individual data lanes and individually identifies which lanes are error-free versus erroneous. Instead of treating the link as a whole, the system divides it into separatable components (lanes) and selectively activates only the functional segments, thereby maintaining maximum throughput using error-free lanes while ensuring reliability by excluding erroneous ones.
Solution Approach 2:
The patent applies local quality by treating each data lane differently based on its specific error status. Rather than uniformly reducing all lanes when any error occurs, the system applies different states (active or inactive) to different lanes based on their local quality characteristics, allowing error-free lanes to continue operating at full capacity while isolating only the problematic lanes.
2Reliability
If the negotiation process renegotiates the number of data lanes, then link reliability is improved, but latency increases
Solution Approach 1:
The patent performs preliminary action by pre-identifying and pre-configuring the error-free data lanes before actual data transmission begins. The system proactively determines which lanes are functional and establishes the optimal link configuration in advance, so that when transmission starts, no time is lost during the actual data transfer phase due to renegotiation.
Solution Approach 2:
The patent applies skipping by rapidly completing the error detection and lane identification process during initialization, then immediately proceeding to data transmission without prolonged renegotiation cycles. The system rushes through the configuration phase to establish the optimal lane set quickly, minimizing the time penalty before high-speed transmission begins.
Data Source
AI summary
Methods and apparatuses are provided that can establish data links with greater bandwidths within die-to-die interconnect architectures. In one example, a system-on-a-chip (SoC) includes an error status register, a plurality of data ports for a data link, and a processor electrically coupled to the error status register and to the plurality of data ports. The processor can receive error data from the error status register and, based on the error data, can determine a portion of the plurality of data ports that are error free. Further, the processor can determine a bandwidth for the data link based on the portion of the plurality of data ports that are error free. Further, the processor can initiate a link negotiation process to establish the link with another device based on the link width value and the portion of the plurality of data ports that are error free.