Die Interconnect Latency Reduction via L2 Fast State
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Solution Overview
Problem
Die-to-die interconnect architectures, such as those defined by the Universal Chiplet Interconnect Express (UCIe) standard, experience significant latencies during link state transitions, particularly when moving from lower power states like L2 to fully operational states, due to the need to go through multiple intermediate states like RESET, sideband initialization, and main-band initialization.
Innovation Solution
The introduction of an 'L2_Fast' or 'enhanced L2' state that allows for the storage of link configuration values in memory during power reduction, enabling direct transition to a power stabilization state upon reactivation, thereby bypassing the RESET and initialization states, and allowing clock stabilization before proceeding to the active state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the device transitions from L2 power management link state through multiple intermediate states (RESET, sideband initialization, main-band initialization, main-band training, link initialization), then the device can reliably initialize all subsystems, but the transition latency becomes excessive
Solution Approach 1:
The patent introduces an enhanced L2 state where configuration values are pre-loaded into a configuration register before entering the low-power state. When exiting L2, the device can directly transition to active state without performing initialization sequences, because the configuration is already prepared in advance. This preliminary action eliminates the need for RESET, sideband initialization, main-band initialization, and link initialization states, reducing latency while maintaining reliability.
2Use of energy by moving object
If the device enters deep power management states to reduce power consumption, then energy efficiency improves, but the time required to reactivate the communication link increases significantly
Solution Approach 1:
The enhanced L2 state implements preliminary action by loading configuration values into a configuration register before the device enters the low-power state. This pre-loading ensures that when the device wakes up, all necessary configuration data is already available in fast memory, eliminating the need for time-consuming initialization sequences during reactivation. The device can transition directly from enhanced L2 to active state, maintaining low power consumption while dramatically reducing reactivation time.
3Use of energy by moving object
If the device saves configuration values in non-volatile memory during L2 state, then power management is improved, but the device must undergo complete re-initialization upon waking, increasing latency
Solution Approach 1:
The patent resolves this contradiction by implementing preliminary action - loading configuration values into a configuration register (fast memory) before the device enters the L2 power management state. This pre-loading strategy ensures that configuration data is preserved in fast memory rather than being written to non-volatile memory. When the device wakes up, the configuration is already available in the register, allowing direct transition to active state without re-initialization, thus maintaining both power management efficiency and fast reactivation.
Data Source
AI summary
Methods and apparatuses are provided to reduce latencies associated with state transitions in die-to-die interconnect architectures. In one example, a physical layer of a die detects a first event indicating a transition to a lower power state. In response to the first event, the physical layer transitions to a lower power state where one or more clock configuration values are read from registers and stored in memory. The physical layer then detects a second event indicating a transition to an active state. In response to the second event, the physical layer reads the clock configuration values from the memory, and writes the clock configuration values to the registers. The physical layer then transitions to a power stabilization state, and remains in the power stabilization state for an amount of time to allow clocks to stabilize. The physical layer then transitions to a training state.