Die-to-Die Interconnect with Sideband/Mainband Link Coordination
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Solution Overview
Problem
Existing interconnect architectures struggle to meet the increasing demands for high-performance computing, particularly in server environments, where communication between multiple processors and devices is critical, and current solutions lack interoperability and flexibility across different vendors and technology nodes.
Innovation Solution
The introduction of the Universal Chiplet Interconnect Express (UCIe) protocol provides a standardized, high-bandwidth, low-latency, and power-efficient die-to-die interconnect that supports multiple protocols, enabling seamless interoperability and flexible integration of chiplets from different vendors and technology nodes, facilitating on-package and off-package connectivity across various computing systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then electrical communications are handled, but communication speed and bandwidth are limited
Solution Approach 1:
The patent segments the interconnect architecture into multiple high-speed serial links instead of using a single multi-drop bus. Each link operates independently at higher speeds, collectively providing greater bandwidth while maintaining electrical communication capabilities. This segmentation resolves the contradiction by enabling faster communication without requiring a completely complex new architecture.
Solution Approach 2:
The patent transitions from traditional electrical domain communication to optical domain communication for interconnect. This dimensional change from electrical signals to optical signals enables significantly higher communication speeds and bandwidth while reducing interference and signal degradation issues inherent in electrical multi-drop buses.
2Adaptability or versatility
If existing interconnect architectures are used, then current communication needs are met, but interoperability across different vendors and technology nodes is lacking
Solution Approach 1:
The patent implements a universal optical interconnect architecture that can accommodate multiple protocols and standards through a common physical layer. This multi-functional design allows different vendors and technology nodes to interoperate reliably by providing a standardized optical interface that transcends specific implementation details, thereby enhancing both adaptability and reliability simultaneously.
3Volume of moving object
If more processing power is integrated into smaller packages, then device size is reduced, but communication demands between components increase
Solution Approach 1:
The patent replaces electrical signal transmission with optical signal transmission for inter-component communication. This substitution eliminates resistive losses and electromagnetic interference inherent in electrical systems, enabling higher communication speeds with lower power consumption. The optical interconnect allows more processing power to be integrated into smaller packages without proportionally increasing power demands.
4Productivity
If communication bandwidth between processors is increased, then computing performance improves, but power consumption increases
Solution Approach 1:
The patent changes the fundamental parameter of signal transmission from electrical to optical domain. This parameter change enables higher communication bandwidth between processors while consuming less power, as optical signals experience no resistive losses and can be transmitted at higher frequencies without proportional increases in power consumption, thereby improving computing performance without the typical power penalty.
Data Source
AI summary
A port is to couple to another die over a die-to-die (D2D) link and includes physical layer (PHY) circuitry including a first number of sideband lanes to carry data for use in training and management of the D2D link, and a second number of mainband lanes to implement a main data path of the D2D link. The mainband lanes include a forwarded clock lane, a valid lane, and a plurality of data lanes. A logical PHY coordinates functions of the sideband lanes and the mainband lanes.