Die Interconnect Architecture With Shared I/O Pin Routing
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Solution Overview
Problem
Die packages require a large number of connections to I/O pins as the number of dies and features increase, leading to increased size and cost, and inefficient use of real estate on printed-circuit-boards.
Innovation Solution
Implementing control logic to share pins among multiple dies within a die package, using control modes to determine how to connect pins to specific dies based on received signals, and allowing direct connections for critical signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of dies within a die package increases, then the functionality and performance of the die package is improved, but the number of connections required to I/O pins increases, resulting in increased size and cost
Solution Approach 1:
Multiple dies share common I/O pins through the substrate, merging the connection resources. Instead of each die having dedicated pins, the pins are combined and shared across multiple dies, reducing the total pin count while maintaining support for multiple dies with enhanced functionality
Solution Approach 2:
The I/O pins are designed to serve multiple functions and multiple dies simultaneously. The same pin can be used by different dies for different signals or the same signal type, making the pin infrastructure universal rather than dedicated to a single die
2Adaptability or versatility
If the number of connections to I/O pins increases, then the number of supported features increases, but the manufacturing cost increases
Solution Approach 1:
The patent merges multiple connection paths through the substrate interconnect structure, allowing multiple dies to share common I/O pins. This reduces the total number of pins required while supporting the same or greater number of features, thereby lowering manufacturing costs
3Quantity of substance
If the die package size increases, then more I/O pins can be accommodated, but the real estate required on printed-circuit-boards increases
Solution Approach 1:
The patent merges the I/O pin requirements of multiple dies into a reduced set of shared pins through the substrate interconnect architecture. This consolidation reduces both the physical size of the die package and the footprint required on the PCB, as fewer pins need to be routed and connected
4Reliability
If dedicated connections are provided for each die, then signal transmission reliability is improved, but the complexity of the interconnect architecture increases
Solution Approach 1:
The patent segments the interconnect function into two parts: dedicated interconnects within the substrate for reliable die-to-die communication, and shared I/O pins for external connections. This segmentation maintains reliability through dedicated paths while reducing overall complexity by sharing external pins
Data Source
AI summary
Methods and apparatuses are provided to improve pin utilization within die architectures. In one example, a die package includes a first pin, a second pin, a first die, a second die, and a third die. The first die is electrically coupled to the first pin over a first interconnect, and to the second pin over a second interconnect. The first die is also electrically coupled to the second die over a third interconnect, and to the third die over a fourth interconnect. The first die is configured to receive a first signal over the first interconnect. Based on the first signal, the first die is configured to electrically connect the second interconnect to either the third interconnect, or the fourth interconnect. A second signal is received over the second interconnect, and is transmitted to the one of the third interconnect and the fourth interconnect electrically connected to the second interconnect.