3D Die Interconnect System for High Speed Low Power Packaging
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Solution Overview
Problem
Current integrated circuit packaging technologies face challenges with planarity issues, limited fanin/fanout capabilities, excessive signal travel paths, signal integrity problems, and increased power consumption due to dense and complex circuit designs, which hinder high-density, high-speed, and low-power packaging.
Innovation Solution
A system and method for interconnecting die using direct and indirect coupling methods, such as conductive contacts, photonic devices, and wireless communications, allowing signals to bypass multiple intervening layers and enabling non-planar connections between die, thereby reducing signal travel length and enhancing fanin/fanout capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional planar packaging and routing methods are used, then manufacturing simplicity is maintained, but signal travel paths become excessively long and power consumption increases
Solution Approach 1:
The patent transitions from traditional planar (2D) packaging to three-dimensional (3D) stacked packaging, where die are vertically stacked and interconnected through vertical vias and through-silicon vias (TSVs). This dimensional change dramatically shortens signal travel paths by eliminating long lateral routes, directly reducing power consumption while accepting increased structural complexity that is managed through systematic via formation and layering techniques.
Solution Approach 2:
The patent implements nested interconnect structures where multiple conducting layers and dielectric layers are stacked within each other, with vias penetrating through multiple layers to establish vertical connections. This nesting approach allows compact integration of multiple interconnect functions within the vertical space, reducing the overall footprint while managing the complexity through hierarchical layer organization.
2Adaptability or versatility
If dense packaging is implemented to increase functionality, then device capability improves, but planarity issues and signal integrity problems worsen
Solution Approach 1:
By stacking die vertically in three dimensions, the patent achieves high functionality and density without compromising planarity at the package level. The vertical interconnection through TSVs and via structures maintains signal integrity by providing direct, controlled-length paths, avoiding the planarity issues that would arise from attempting to route dense connections in a single plane.
Solution Approach 2:
The patent introduces intermediary structures including dielectric layers, conducting layers, and via structures that mediate between stacked die. These intermediaries provide controlled impedance paths, electrical isolation, and mechanical support, ensuring signal integrity while enabling dense vertical integration. The systematic use of alternating dielectric and conducting layers acts as intermediaries to manage signals between stacked functional blocks.
3Productivity
If multiple conducting layers are used to increase interconnect density, then fanin/fanout capability improves, but manufacturing complexity increases
Solution Approach 1:
The patent achieves high fanin/fanout capability by utilizing multiple conducting layers stacked vertically, where each layer can carry independent signals. This vertical stacking provides massive interconnect capacity without requiring complex lateral routing. The manufacturing complexity is managed through standard semiconductor fabrication processes that form multiple layers sequentially, with each layer built using established techniques.
Solution Approach 2:
The patent segments the interconnect function across multiple conducting layers, with each layer handling specific signal routes. This segmentation allows independent optimization and fabrication of each layer, reducing overall manufacturing complexity. The systematic alternation of dielectric and conducting layers creates a modular structure where each pair can be formed using standardized process modules.
Data Source
AI summary
A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include active and passive elements. In one embodiment there is at least one interconnect coupling at least one conducting layer on a side of one die to at least one conducting layer on a side of the other die. Another interconnect embodiment is a slug having conducting and dielectric layers disposed between two or more die to interconnect between the die. Other interconnect techniques include direct coupling such as rod, ball, dual balls, bar, cylinder, bump, slug, and carbon nanotube, as well as indirect coupling such as inductive coupling, capacitive coupling, and wireless communications. The die may have features to facilitate placement of the interconnects such as dogleg cuts, grooves, notches, enlarged contact pads, tapered side edges and stepped vias.