Circuit Die Isolation Test Structure for Buffer Leakage Screening
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Solution Overview
Problem
Integrated circuits, particularly those using gallium nitride (GaN) on silicon carbide (SiC) substrates, face challenges with cross-wafer variation in electrical isolation at the buffer layer, leading to significant leakage current due to non-idealities in the buffer layer. Additionally, the difficulty in etching SiC substrates can impact the quality of through-substrate vias (TSVs) formed in these substrates.
Innovation Solution
The integration of an isolation test structure (ITS) within the integrated circuit, which includes buffer layer structures and through-substrate vias (TSVs), allows for the validation of electrical isolation at the buffer layer level for each individual integrated circuit die. This ITS correlates the resistance of the test structure with the resistivity of the buffer layer, enabling precise identification and rejection of integrated circuit dies with unacceptable isolation before packaging.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional region-based characterization is used, then manufacturing complexity is reduced, but measurement precision deteriorates
Solution Approach 1:
The patent divides the wafer-level characterization into individual die-level measurements by incorporating isolation test structures on each die. This segmentation allows precise measurement of electrical isolation for each die independently, resolving the contradiction between measurement precision and device complexity by enabling per-device validation without requiring complex wafer-level mapping systems.
Solution Approach 2:
Each die contains its own isolation test structure that enables self-validation of electrical isolation properties. The test structure includes buffer layer structures and TSVs that are specific to each die, allowing the die to characterize itself without external wafer-level equipment, thereby improving measurement precision while avoiding complex characterization systems.
2Ease of manufacture
If SiC substrate etching is performed, then TSV formation is achieved, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary characterization of TSV quality using the isolation test structure before final device assembly. By measuring electrical isolation through the TSVs early in the process, defects can be identified and rejected promptly, preventing waste of subsequent manufacturing steps and improving overall manufacturing efficiency despite the time-consuming SiC etching process.
3Reliability
If buffer layer non-idealities are present, then leakage current increases, but electrical isolation deteriorates
Solution Approach 1:
The isolation test structure enables preliminary detection of buffer layer non-idealities and associated leakage current before final device assembly. By measuring electrical isolation characteristics through the test structure, dies with poor buffer layer quality can be identified and rejected early, preventing defective devices from proceeding to packaging and ensuring high reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of the ITS within each integrated circuit die enables on-wafer per-device validation of electrical isolation, reducing product costs by identifying and rejecting defective dies earlier in the process. This approach improves the precision and accuracy of validation compared to conventional techniques that rely on characterizing entire regions of a wafer.
Implementation Method 1
A resistance of the isolation test structure correlates to a resistivity of the buffer layer
Data Source
AI summary
An integrated circuit includes an isolation test structure (ITS) formed in a non-active region. An electrical isolation between structures of the integrated circuit may be validated based on a measured resistance or conductivity across the ITS. In some embodiments the ITS includes interdigitated buffer layer structures. In some embodiments, the ITS is arranged in series with a test Through-substrate via (TSV). The test TSV is formed with a slower etch rate and smaller diameter than other standard TSVs of the integrated circuit and can be used to validate the formation of the standard TSVs based on measured resistance or conductivity thereof. By arranging the ITS and the test TSV in series, isolation of the integrated circuit and formation of TSVs in the integrated circuit can be validated using a single measurement.