Die-Last RDL Structure for High-Density Chip Interconnects
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Solution Overview
Problem
Conventional multi-chip module technologies face limitations in increasing chip-to-chip interconnects due to minimum line spacing constraints, mechanical stress from low-temperature polyimide films, and challenges in accurately placing expensive fully fabricated chips, which restricts the number of RDL layers and efficiency in processor die interconnects.
Innovation Solution
The die-last process flow is adopted, where interconnect chips are mounted after RDL construction, allowing for high-temperature RDL dielectrics and enabling more RDL layers, and using a redistribution layer (RDL) structure with polybenzoxazole dielectric layers to buffer stress and facilitate efficient chip interconnects, along with molding layers for accurate chip placement and reduced waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional 2D WLFO technology is used with low-temperature polyimide films, then chip placement is facilitated, but mechanical stress increases and the number of RDL layers is limited
Solution Approach 1:
The patent changes the temperature parameter for RDL dielectric curing from low-temperature (conventional polyimide) to high-temperature (polybenzoxazole), enabling higher thermal stability and reduced mechanical stress while supporting more RDL layers. This parameter change allows the system to achieve both ease of chip placement and reduced mechanical stress.
2Productivity
If more RDL layers are added to increase chip-to-chip interconnects, then interconnect efficiency improves, but manufacturing complexity and temperature-related limitations increase
Solution Approach 1:
The patent applies preliminary action by constructing the RDL structure with multiple layers and polybenzoxazole dielectric layers before mounting the chips. This allows the complex RDL interconnect structure to be fabricated in advance with high-temperature processing, avoiding temperature-related limitations during chip mounting and enabling more interconnect layers without increasing overall manufacturing complexity.
3Manufacturing precision
If fully fabricated chips are mounted early in the process, then chip placement accuracy can be optimized, but the number of subsequent process steps is limited and yield issues cannot be detected until late
Solution Approach 1:
The patent inverts the conventional sequence by mounting chips after RDL construction rather than before. This inversion allows chips to be placed on an already-fabricated RDL structure with precise positioning, while enabling early detection of yield issues in the RDL fabrication process itself. The inversion resolves the contradiction by achieving both placement accuracy and process efficiency through sequential rather than simultaneous optimization.
4Ease of manufacture
If conventional multi-chip module technologies are used, then manufacturing processes are established, but minimum line spacing constraints restrict the number of interconnects
Solution Approach 1:
The patent transitions from 2D WLFO to 3D WLFO by stacking multiple RDL layers vertically. This dimensional change allows interconnects to be routed through multiple layers, effectively increasing the number of chip-to-chip interconnects beyond what is possible with minimum line spacing constraints in a single 2D plane. The vertical dimension provides additional routing paths while maintaining manufacturing process stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of chip-to-chip interconnects, reduces mechanical stress, and allows for the use of off-the-shelf high-bandwidth memory chips, optimizing chip placement accuracy and minimizing yield issues, while enabling more RDL layers without temperature-related limitations.
Implementation Method 1
using a redistribution layer (RDL) structure with polybenzoxazole dielectric layers to buffer stress
Data Source
AI summary
Various multi-die arrangements and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing a semiconductor chip device is provided. A redistribution layer (RDL) structure is fabricated with a first side and second side opposite to the first side. An interconnect chip is mounted on the first side of the RDL structure. A first semiconductor chip and a second semiconductor chip are mounted on the second side of the RDL structure after mounting the interconnect chip. The RDL structure and the interconnect chip electrically connect the first semiconductor chip to the second semiconductor chip.