Die Layout Conversion to Chip-Scale Package Grid
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Solution Overview
Problem
Existing IC designs optimized for leadframe packaging are difficult to convert to chip-scale packaging without significant redesign, which complicates the adaptation process and may affect IC performance.
Innovation Solution
The conversion involves overlaying a standard ball-site frame on the IC's layout to identify optimal bonding pad locations, allowing the use of existing metal masks with new masks created for bonding pads and routing layers to align with a standard grid, enabling chip-scale packaging without altering the original circuitry masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If existing IC designs optimized for leadframe packaging are converted to chip-scale packaging, then the footprint on PCB is minimized and packing density is improved, but the conversion process requires significant redesign and may affect IC performance
Solution Approach 1:
The patent applies preliminary action by pre-defining a ball-site frame grid overlay on the die layout before final pad placement. This allows the bonding pad locations to be predetermined according to standard ball grid array positions (0.3mm or 0.5mm pitch), enabling the conversion from leadframe to chip-scale packaging without requiring complete redesign of the IC circuitry. The pre-established grid system guides the placement of bonding pads at optimal locations that align with standard PCB ball sites.
2Adaptability or versatility
If bonding pads are relocated to align with standard ball grid array positions, then adaptability to chip-scale packaging is improved, but the original circuitry layout optimized for leadframe packaging may be compromised
Solution Approach 1:
The patent applies local quality by making targeted modifications only at specific locations where bonding pads are needed, rather than redesigning the entire IC layout. The ball-site frame overlay identifies specific grid positions where bonding pads should be placed, and metal masks are modified only at these localized areas to create pads and routing layers. The rest of the circuitry maintains its original leadframe-optimized layout, preserving its performance characteristics while adding chip-scale packaging compatibility at critical locations.
Data Source
AI summary
A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.