Die-Level Block Family Error Avoidance for Memory
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Solution Overview
Problem
Existing memory sub-systems face challenges in effectively managing die-to-die variations in slow charge loss (SCL) and temporal voltage shift (TVS), leading to high bit error rates and trigger rates.
Innovation Solution
The implementation of die-level block family error avoidance techniques, where each die in a memory device generates a customized block family error avoidance data structure based on individual SCL characterization, allowing for precise tracking and mitigation of TVS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die-level block family error avoidance techniques are implemented with customized data structures, then bit error rates and trigger rates improve, but device complexity increases
Solution Approach 1:
The patent segments the memory system into die-level units, where each die generates and maintains its own customized block family error avoidance data structure. This segmentation allows independent error avoidance strategies for each die, improving reliability without requiring system-wide complexity increases.
Solution Approach 2:
Each die is provided with customized error avoidance parameters tailored to its specific slow charge loss characteristics. This local quality approach ensures that each die operates with optimally tuned error avoidance settings, improving bit error rates while keeping the complexity localized to individual dies rather than the entire memory subsystem.
2Reliability
If die-specific error avoidance strategies are implemented, then reliability improves, but manufacturing complexity increases
Solution Approach 1:
The customized block family error avoidance data structures are generated during manufacturing or initialization based on measured slow charge loss characteristics of each die. This preliminary action captures die-specific variations upfront, enabling reliable operation without requiring complex real-time adjustments during manufacturing or operation.
Solution Approach 2:
Each die autonomously generates its own error avoidance data structure based on its inherent slow charge loss characteristics. This self-service approach eliminates the need for complex external characterization equipment or procedures, simplifying manufacturing while improving reliability through die-specific optimization.
Data Source
AI summary
A sacrificial block in a die of a plurality of dies of a memory device is identified. Responsive to performing a data retention test on the sacrificial block, a threshold voltage shift of at least one logical programming level of the sacrificial block is identified. A block family error avoidance data structure is generated for the die of the plurality of dies comprising a plurality of read level offsets based on the threshold voltage shift.