Die-Level Via Test Structure for Accurate Open Via Detection
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Solution Overview
Problem
Conventional methods for detecting open vias in integrated circuit dies are time-consuming and inaccurate, leading to over-rejection of good dies and reduced yield due to blanket rejection techniques.
Innovation Solution
Incorporating a Design for Manufacturing (DFM) structure into each die to detect open vias using current and voltage measurements, allowing for precise identification of defective and progressively failing dies on a granular level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If C-SAM is used to detect open vias, then detection capability is provided, but time consumption increases and measurement accuracy decreases
Solution Approach 1:
The patent divides the via detection task into two segments: (1) electrical testing identifies defective dies with open vias, and (2) DFM structures provide localized acoustic measurement at specific locations. This segmentation allows rapid electrical testing while using acoustic microscopy only where needed, reducing overall detection time and improving accuracy compared to blanket acoustic scanning.
Solution Approach 2:
The patent introduces DFM structures as intermediary elements that bridge electrical testing and acoustic microscopy. These structures include acoustic windows and reference structures that enable localized acoustic measurement at specific via locations, allowing precise open via detection without requiring time-consuming blanket acoustic scanning of the entire wafer.
2Ease of manufacture
If blanket rejection of dies at wafer edge is applied, then open via detection is simplified, but die yield decreases due to over-rejection
Solution Approach 1:
The patent applies local quality by placing DFM structures at specific locations (wafer edges and interior regions) where open vias are most likely to occur. This allows targeted acoustic measurement only where needed, rather than blanket rejection of all edge dies. The localized approach maintains detection simplicity while significantly improving die yield by preserving good dies that would be incorrectly rejected.
Solution Approach 2:
The patent implements feedback through the DFM structures that provide real-time information about via integrity at specific locations. The acoustic measurement results feed back to the testing system, allowing precise identification of defective dies with open vias while preserving good dies. This feedback mechanism replaces blanket rejection with informed, localized decision-making, improving both simplicity and yield.
3Productivity
If conventional electrical testing is used, then die testing is performed, but open vias are not accurately detected
Solution Approach 1:
The patent merges electrical testing and acoustic microscopy into a unified testing approach. Electrical testing is performed first to identify candidate defective dies, then DFM structures provide localized acoustic confirmation at specific via locations. This combination maintains high testing throughput while significantly improving open via detection accuracy, as acoustic microscopy provides definitive verification that electrical testing alone cannot achieve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances die yield by accurately identifying open vias and reducing the rejection of good dies, improving the manufacturing process efficiency.
Implementation Method 1
The DFM structure may include a current and voltage measurement to identify an open via
Data Source
AI summary
Systems and methods for using a design for manufacturing (DFM) structure to detect an open via. The DFM structure comprises a resistor, one or more vias between a first pin and a second pin, and a transistor. A voltage from a voltage source is applied to the DFM structure that causes a current to flow across the resistor, the one or more vias and the transistor, such that the value of the current indicates an open or closed via.