Die-Level WAT Prediction for Wafer Testing Yield Analysis
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Solution Overview
Problem
Conventional wafer-level Wafer Acceptance Test (WAT) methods are limited by small sample sizes, leading to inaccurate and incomplete AI analysis, and struggle to address non-uniform defect distributions and the trade-off between System Level Test (SLT) yield and chip performance.
Innovation Solution
A machine learning-based system that collects actual WAT measurement parameters from multiple locations on a wafer and uses sensors within the wafer to predict die-level WAT parameters, employing a two-stage framework for enhanced analysis, including die-level WAT data prediction and key factor identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If wafer-level WAT data is used for AI analysis, then the analysis can be performed with existing testing infrastructure, but the sample amount is limited and accuracy is reduced
Solution Approach 1:
The patent segments the wafer-level WAT data into die-level measurements by dividing the wafer into multiple measurement locations (e.g., 9 locations). Each location provides independent WAT data for multiple dies, transforming the data structure from wafer-level aggregates to die-level individual measurements. This segmentation increases the effective sample amount from 2000 wafer-level samples to potentially thousands of die-level samples while maintaining measurement precision through location-specific analysis.
2Productivity
If device speed is adjusted to increase SLT yield, then SLT yield improves, but chip performance decreases
Solution Approach 1:
The patent applies local quality by analyzing WAT parameters at specific measurement locations on the wafer and identifying location-specific trends. By determining which locations have higher defect rates or performance characteristics, the system can target process adjustments to specific regions rather than applying uniform changes across the entire wafer. This allows optimization of SLT yield at locations where it is most needed while preserving chip performance at locations where speed adjustments would be most harmful.
Data Source
AI summary
A machine learning-based wafer testing yield boosting method includes acquiring a plurality of actual Wafer Acceptance Test (WAT) measurement parameters at a plurality of locations on a wafer from a foundry and a plurality of WAT sensing parameters monitored by a plurality of sensors disposed within the wafer, and inferring a plurality of predicted WAT parameters for a plurality of dies on the wafer based on the plurality of actual WAT measurement parameters and the plurality of WAT sensing parameters by a machine learning model.