Die-to-Die Link Bring-Up with Sideband and Mainband Training

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Solution Overview

Problem

Current die-to-die interconnects in multi-chip packaging face challenges with high bit error rates and long latencies due to inefficient error correction and retry operations, hindering performance growth and die disaggregation.

Innovation Solution

A multi-protocol capable, on-package interconnect protocol (UCIe) with an ordered bring-up flow for sideband and mainband initialization, including lane reversal and repair, to enable faster initialization and redundancy, supporting various communication protocols like PCIe and CXL, and allowing for die rotation and mirroring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If current die-to-die interconnect techniques are used, then high data rates can be achieved, but long latencies occur due to retries and error correction operations

Engineering Contradiction:
Improvedata rateVSAvoidlatency
Core Design Contradiction:
SpeedVSLoss of time

Solution Approach 1:

The patent performs lane reversal detection and repair operations during the initialization phase before normal data transmission begins. By detecting reversed lanes and applying corrections in advance, the system prevents latency issues during actual data communication, thus maintaining high data rates while reducing transmission delays.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interconnect initialization process is segmented into distinct phases: reset detection, lane reversal detection, lane repair, and normal operation. This segmentation allows error correction and retry operations to be isolated to specific initialization stages rather than occurring continuously during data transmission, thereby reducing overall latency while maintaining high data rates.

Inventive Principle:
Principle #1Segmentation

2Productivity

If die disaggregation is implemented in multi-chip packaging, then performance growth and complex product creation are enabled, but high bit error rates and long latencies burden operating speeds

Engineering Contradiction:
Improveperformance growthVSAvoidbit error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary lane reversal detection and repair operations during the initialization phase before normal disaggregated die communication begins. This preliminary action corrects potential connection issues between dies in advance, ensuring high reliability for bit error rates during actual data transmission while enabling performance growth through die disaggregation.

Inventive Principle:
Principle #10Preliminary action

3Ease of manufacture

If lane reversal and repair operations are performed, then yield loss is reduced and die rotation/mirroring is enabled, but device complexity increases

Engineering Contradiction:
Improveyield lossVSAvoidinitialization complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The initialization process is segmented into distinct detectable states: reset detection, lane reversal detection, and repair operations. This segmentation enables systematic handling of die rotation and mirroring scenarios through standardized procedures, reducing yield loss while managing complexity through structured initialization sequences rather than ad-hoc corrections.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs self-diagnosis and self-correction during initialization by automatically detecting lane reversals and applying repair operations without external intervention. This self-service capability enables die rotation and mirroring compensation while reducing yield loss, with the complexity confined to the automated initialization routine rather than requiring complex external control systems.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12405912B2Link initialization training and bring up for die-to-die interconnect
Publication Date: 2025.09.02 INTEL CORP
  • US12405912B2 patent drawing
  • US12405912B2 patent drawing
  • US12405912B2 patent drawing

AI summary

In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.