Die Location Compensation in Stacked Semiconductor Devices

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Solution Overview

Problem

In semiconductor devices with stacked integrated circuit die, propagation delays in coupling signals between external electrical connectors and die lead to skewed data eyes, output slew rate skew, and impedance mismatches, making it difficult for external devices to correctly latch read data, especially as distance from connectors increases.

Innovation Solution

A semiconductor device with a clock circuit using a delay lock loop and a feedback model delay unit, along with switchable delays and a compensation circuit, to synchronize clock signals across multiple die, compensating for disparate propagation delays and impedance variations by adjusting signal timing and drive strength based on die location.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple semiconductor die are stacked to increase device functionality and integration, then device capability and signal processing capacity are improved, but propagation delays between external connectors and die increase causing skewed data eyes and synchronization issues

Engineering Contradiction:
Improvedevice capabilityVSAvoidpropagation delay
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by measuring and storing propagation delay characteristics for each die location in the stack during manufacturing or initialization. These pre-measured delay values are stored in lookup tables within each die, enabling the system to compensate for propagation delays without real-time measurement. When a die receives a clock signal, it uses its pre-stored delay compensation value to adjust its output timing, thereby resolving the synchronization issue caused by varying propagation delays in stacked configurations.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If die are positioned at different distances from external electrical connectors, then device functionality is maintained, but impedance mismatches and slew rate variations occur affecting signal integrity

Engineering Contradiction:
Improvedevice functionalityVSAvoidsignal integrity
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies local quality by implementing location-specific compensation circuits and parameters for each die in the stack. Each die contains compensation circuitry with adjustable delay elements and slew rate control mechanisms tailored to its specific position relative to external connectors. Dies farther from connectors use different compensation values than those closer to connectors, ensuring that each die operates with optimized signal characteristics for its local environment, thereby maintaining consistent signal integrity across all die regardless of position.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If delay lock loop is used to synchronize clock signals within each die, then internal timing is improved, but disparate propagation delays between die and external connectors remain uncompensated

Engineering Contradiction:
Improveinternal timingVSAvoidexternal propagation delay
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent extends the feedback mechanism by having each die measure its own clock signal propagation delay from the external connector through its internal circuitry, then use this measured delay information to adjust its output timing. The delay lock loop within each die operates with an extended feedback path that accounts for external connector delays, allowing each die to synchronize its operations with the external interface despite varying distances. This creates a distributed feedback system where each die independently compensates for its specific propagation delay.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP2471180B1Die location compensation
Publication Date: 2020.10.07 MICRON TECHNOLOGY INC
  • EP2471180B1 patent drawingFigure 1~2
  • EP2471180B1 patent drawingFigure 3
  • EP2471180B1 patent drawingFigure 4

AI summary

Embodiments are described that compensate for a difference in a characteristic (e.g., of performance or operation) of a semiconductor device that is a function of the location of a die in a device. In one embodiment, a clock circuit may generate a clock signal having a timing that varies with the location of a die so that signals are coupled from the die to a substrate at the same time despite differences in the signal propagation time between the substrate and the various die. In other embodiments, for example, differences in the termination impedance or driver drive-strength resulting from differences in the location of a die in a stack may be compensated for. Other embodiments are also disclosed.