Die Memory Fault Detection Using Consolidated ECC Status
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Solution Overview
Problem
Existing die architectures face challenges in efficiently detecting memory faults due to data errors, which are costly in terms of die real estate and require multiple signals, and current error correction mechanisms are inefficient.
Innovation Solution
A processor-based system generates a consolidated error correcting code and status for multiple data words, reducing the need for individual error correcting codes and memory addresses, thereby minimizing die real estate and signal requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction mechanisms are used for each data word, then data error detection capability is improved, but die real estate usage increases significantly
Solution Approach 1:
The patent merges error correction resources by implementing a single error correcting code generator that serves multiple data words (e.g., 4 data words) instead of having separate generators for each data word. This consolidation reduces the number of error correcting code generators from N to 1, thereby reducing die real estate usage while maintaining error detection capability across all data words through a shared error status signal.
2Measurement precision
If individual error correcting codes are generated for each data word, then error detection precision is improved, but signal overhead increases
Solution Approach 1:
The error status signal generated by the single error correcting code generator serves multiple functions: it indicates errors for all data words simultaneously, enables centralized error detection, and triggers appropriate error handling. This universal error status signal replaces multiple individual error signals, reducing signal overhead while maintaining the ability to detect errors in each data word through the shared monitoring mechanism.
Data Source
AI summary
Methods and apparatuses directed to memory fault detection mechanisms within die architectures. In some examples, a die package includes decoder logic that receives multiple data words, and a first error correcting code for each of the data words. The decoder logic generates, for each of the data words, a second error correcting code based on a corresponding one of the data words. Further, the decoder logic generates, for each of the data words, an error status based on the first error correcting code and the second error correcting code that corresponds to each of the data words. The die package also includes error generation logic that receives the error status for the data words from the decoder logic, and generates error data based on a combination of the error statuses for the data words. The error generation logic can store the error data in a memory device.