Integrated Die Mounting Structure for Electrical Isolation

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Solution Overview

Problem

Existing integrated device packages face challenges in providing adequate electrical isolation between the carrier and integrated device die, leading to potential shorting and stress issues due to stacking, which current technologies have not adequately addressed.

Innovation Solution

A multi-layer mounting structure comprising a first insulating adhesive layer and a spacer layer between the integrated device die and the carrier, which physically and electrically isolates bond wires from the die, reducing the risk of shorting and stress by using materials with closely matched thermal expansion coefficients.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the integrated device die is stacked on the carrier, then the integration density is improved, but electrical isolation between the carrier and die deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a mounting structure comprising an insulating adhesive layer and a spacer as intermediary elements between the carrier and integrated device die. The insulating adhesive layer provides electrical isolation while bonding the components, and the spacer maintains physical separation to prevent wire bond contact with the die, thus resolving the electrical isolation issue while maintaining high integration density through stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The mounting structure uses composite materials including insulating adhesive layer (such as epoxy-based materials) and spacer materials with specific dielectric properties. These composite materials provide both mechanical bonding functionality and electrical isolation properties simultaneously, enabling the stacked configuration to achieve both high integration density and reliable electrical isolation.

Inventive Principle:
Principle #40Composite materials

2Productivity

If the integrated device die is stacked on the carrier, then the integration density is improved, but stress on the carrier deteriorates

Engineering Contradiction:
Improveintegration densityVSAvoidstress on carrier
Core Design Contradiction:
ProductivityVSStress or pressure

Solution Approach 1:

The patent employs materials for the mounting structure with closely matched thermal expansion coefficients to both the carrier and the integrated device die. This parameter matching reduces thermally-induced stress during temperature cycling and processing, allowing the stacked configuration to achieve high integration density without excessive stress on the carrier.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The insulating adhesive layer and spacer act as intermediary elements that distribute and reduce stress transmission between the carrier and the integrated device die. These compliant mounting structures absorb thermal expansion mismatches and mechanical stresses, protecting the carrier from stress-induced failures while enabling high-density stacking.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If wire bonding is used to connect the carrier to the package substrate, then electrical connection is improved, but the risk of shorting deteriorates

Engineering Contradiction:
Improveelectrical connectionVSAvoidrisk of shorting
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The spacer serves as an intermediary barrier that physically separates the wire bonds from the integrated device die. This spatial separation prevents direct contact between conductive wire bonds and the die, eliminating the shorting risk while maintaining electrical connection functionality through proper wire bond routing around or above the spacer.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The spacer introduces a vertical dimension of separation, lifting the wire bonds away from the die surface in the Z-direction. This dimensional separation provides electrical isolation in the vertical space while allowing horizontal wire bond routing to maintain electrical connections, thus resolving the shorting risk without compromising electrical connectivity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces the risk of electrical shorting and stress-induced failures in integrated device packages by ensuring electrical isolation and stress reduction, while also enhancing electrical and thermal performance through the use of materials with matched thermal expansion coefficients.

Implementation Method 1

a multi-layer mounting structure comprising a first insulating adhesive layer and a spacer layer between the integrated device die and the carrier, which physically and electrically isolates bond wires from the die

Methodology Applied
Scientific EffectElectrical insulation: Electrical Resistance

Implementation Method 2

reducing the risk of shorting and stress by using materials with closely matched thermal expansion coefficients

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentEP3553819B1Mounting structures for integrated device packages
Publication Date: 2025.07.09 ANALOG DEVICES INT UNLTD CO
  • EP3553819B1 patent drawingFigure 1A~1B
  • EP3553819B1 patent drawingFigure 2A~2C
  • EP3553819B1 patent drawingFigure 3A~3C

AI summary

An integrated device package is disclosed. The package includes a carrier (3) and an integrated device die (2') having a front side and a back side. A mounting structure serves to mount the back side of the integrated device die (2') to the carrier (3). The mounting structure comprises a first layer (4) over the carrier (3) and a second element (13) between the back side of the integrated device die (2') and the first layer (4). The first layer (4) comprises a first insulating material that adheres to the carrier (3), and the second element (13) comprises a second insulating material.