Semiconductor Die Overlay Correction for RDL Alignment Shift Control
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Solution Overview
Problem
Semiconductor die movement during packaging leads to alignment issues in forming redistribution layers, resulting in reduced yields due to misalignment and potential electrical shorting, especially as integration densities increase.
Innovation Solution
Implementing an overlay measurement and correction process using metrology tools to adjust the position of semiconductor dies on a temporary carrier before encapsulation, and compensating for non-linear shifts during the formation of redistribution layers to ensure accurate alignment and prevent misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor dies are positioned on carrier wafers and insulating material is formed to cover the semiconductor dies, then wafer level packaging is achieved, but undesirable movement of the semiconductor dies occurs causing alignment problems in subsequently formed RDL layers
Solution Approach 1:
The patent applies preliminary action by performing overlay measurement and correction on semiconductor dies before they are permanently encapsulated in the insulating material. Metrology tools measure the positions of conductive connectors and contact pads, and corrections are made to compensation values that will be used during subsequent RDL formation processes. This advance measurement and correction prevents alignment issues from developing during packaging.
Solution Approach 2:
The patent implements feedback by using metrology tools to continuously measure the positions of conductive connectors and contact pads on semiconductor dies, calculating overlay offsets, and adjusting compensation values based on these measurements. The measured overlay values feed back into the alignment process, allowing real-time correction of positioning errors that occur during die placement on carrier wafers, thereby maintaining manufacturing precision throughout the packaging process.
2Productivity
If integration densities are increased to meet demand for smaller electronic devices, then more creative packaging techniques are required, but misalignment and electrical shorting increase resulting in reduced yields
Solution Approach 1:
The patent replaces mechanical alignment methods with metrology-based measurement and computational correction systems. Instead of relying solely on mechanical precision during die placement, the system uses optical or electromagnetic metrology tools to measure conductor positions, calculates overlay offsets, and applies computational corrections to alignment data. This substitution enables higher integration densities while maintaining reliability by providing more precise measurement and correction capabilities than mechanical methods alone.
Solution Approach 2:
The patent applies parameter changes by measuring and correcting overlay offset values that represent the positional relationship between conductive connectors and contact pads. By adjusting these compensation parameters based on actual measurements, the system adapts to variations in die placement positions, enabling higher integration densities without compromising yield. The correction values modify the alignment parameters used in subsequent RDL formation processes.
Data Source
AI summary
A shift control method in manufacture of semiconductor device includes: calculating a difference of a relative position between a conductive connector of a semiconductor die and a conductive pad of the semiconductor die relative to a reference mark on the semiconductor die; placing the semiconductor die over a carrier, wherein the difference is compensated when placing the semiconductor die over the carrier; and forming a lithographic pattern on the conductive connector of the semiconductor die.