Homogeneous Die Package JTAG Testing Without Extra Pins
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Solution Overview
Problem
The increasing integration of circuits on a single die in semiconductor manufacturing leads to challenges in standardizing tests, reducing the number of connection balls available for basic operations, and decreasing chip performance due to the allocation of balls for tests.
Innovation Solution
A package circuit with a JTAG interface that allows for various test modes, including serial, parallel, and individual testing of homogeneous dies using four or five signal terminals, without additional pins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If connection balls are allocated for testing, then test capability is improved, but the number of balls available for basic operations decreases
Solution Approach 1:
The JTAG interface serves dual purposes: it provides standardized test capability for homogeneous dies while simultaneously functioning as a communication interface for basic package operations. This multi-functionality allows the same connection balls to be used for both testing and operational purposes, eliminating the need for separate dedicated test balls.
Solution Approach 2:
The patent utilizes the existing JTAG interface parameters (TCK, TMS, TDI, TDO, TRST) to implement multiple test modes (serial test, parallel test, individual die test) by changing the operational state and configuration of these parameters rather than adding new physical connection balls. This allows flexible test capabilities without increasing the number of required connection balls.
2Productivity
If multiple test modes are implemented, then test efficiency is improved, but device complexity increases
Solution Approach 1:
The JTAG interface is designed to perform multiple test functions (serial testing, parallel testing, individual die testing) through a single unified interface structure. By making the interface universal and mode-configurable rather than dedicated to specific test types, the patent achieves high test efficiency without proportionally increasing device complexity.
Solution Approach 2:
The test interface dynamically switches between different test modes (serial, parallel, individual) based on control signals and configuration settings. This dynamic reconfigurability allows the same hardware structure to adapt to different testing requirements, improving test efficiency while avoiding the need for separate dedicated hardware for each test mode.
3Reliability
If additional pins are added for testing, then test capability is improved, but chip performance decreases
Solution Approach 1:
The patent reuses the existing JTAG interface pins for both standardized testing of homogeneous dies and basic package operational communication. This eliminates the need for additional dedicated test pins, thereby preserving chip performance while maintaining comprehensive test capability through intelligent multi-functional utilization of existing resources.
Data Source
AI summary
Provided is a package circuit including a plurality of homogeneous dies including a plurality of input/output terminals, and a joint test action group (JTAG) interface configured to transfer test signals applied to at least one of the plurality of homogeneous dies, wherein a test mode of the plurality of homogeneous dies operates in at least one of a first mode configured to test in series at least two dies among the plurality of homogeneous dies, a second mode configured to test in parallel at least two or more dies among the plurality of homogeneous dies, and a third mode configured to test individually any one die among the plurality of homogeneous dies, and wherein the JTAG interface includes four or five signal terminals.