Semiconductor Die Package With Laser-Structured Low-Inductance Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge of efficient heat dissipation and high-current conduction in miniaturized semiconductor power devices, particularly wide bandgap semiconductors like SiC and GaN, is exacerbated by design-rule limitations and insufficient frontside interconnects, leading to overheating and limited current output.
Innovation Solution
A method involving laser-assisted structuring of metallic structures on semiconductor dies to create frontside and backside electrical conductors, allowing for additive manufacturing of thick interconnects with low inductance, enabling efficient double-side cooling and relaxed design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the source pad area is reduced to accommodate miniaturized chip sizes, then the chip size is reduced, but the heat dissipation capability and current handling become insufficient
Solution Approach 1:
The patent applies 3D vertical stacking to extend the source pad area into the vertical dimension, creating multiple stacked source pads (e.g., 5 stacked source pads) that increase the effective heat dissipation and current handling area without increasing the chip's footprint area, thus resolving the contradiction between miniaturization and thermal management
Solution Approach 2:
The source pad is segmented into multiple stacked segments (multiple source pads vertically stacked), where each segment can independently contribute to heat dissipation and current handling, effectively increasing the total functional area while maintaining a compact chip footprint
2Volume of moving object
If the source pad area is reduced for miniaturization, then the chip size is reduced, but the electric current handling capability decreases
Solution Approach 1:
Multiple source pads are stacked vertically to increase the total current handling area in the vertical dimension, allowing high current paths to be formed through multiple parallel channels without increasing the horizontal footprint, thus maintaining high power handling in miniaturized chips
Solution Approach 2:
Multiple source pads are electrically connected in parallel to combine their current handling capabilities, creating a unified high-current path that can handle substantial electric current while occupying minimal chip area
3Ease of manufacture
If design rules require large clearance around source pad for clip soldering, then the manufacturing is simplified, but the remaining source pad area for cooling and current becomes very small
Solution Approach 1:
The source pad structure transitions from a 2D planar layout to a 3D vertical stack, allowing the effective source pad area to be increased vertically while reducing the horizontal footprint, thus providing sufficient area for cooling and current handling even with required clearances
Solution Approach 2:
The source pad is divided into multiple stacked segments that can be independently formed and connected, allowing the interconnect structure to wrap around and connect to multiple segments, effectively increasing the electrical connection area while maintaining compact dimensions
4Speed
If conventional interconnect structures are used for high switching speeds, then the manufacturing is standard, but the inductance is too high
Solution Approach 1:
The interconnect structure utilizes vertical stacking to create short, direct current paths with minimal loop area, significantly reducing inductance compared to conventional planar interconnects, thus enabling high switching speed operation with low inductance
Solution Approach 2:
The interconnect is segmented into multiple vertical sections that are stacked and connected, creating multiple parallel current paths that reduce overall inductance through parallel path effects and shorter current loops
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances heat dissipation and current conduction capabilities while reducing inductance, allowing for robust and efficient cooling solutions even with small contact pads, thus addressing the limitations of miniaturized semiconductor devices.
Implementation Method 1
Irradiating at least a portion of the metallic material with a laser beam
Implementation Method 2
The laser beam is moved along the second contact pad and/or along the first contact pad in a predetermined pattern so that portions of the metallic material are melted and structured
Data Source
AI summary
A semiconductor die package includes a semiconductor transistor die having a contact pad on an upper main face. The semiconductor die package also includes an electrical conductor disposed on the contact pad and fabricated by laser-assisted structuring of a metallic material, and an encapsulant covering the semiconductor die and at least a portion of the electrical conductor.