Die-to-Die Package Thermal Vias for Heat Dissipation Isolation

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Solution Overview

Problem

The semiconductor industry faces challenges in heat dissipation as the integration density of electronic components increases, leading to thermal management issues in integrated circuit packages.

Innovation Solution

The introduction of thermal vias around the bonding interface between adjacent semiconductor dies, which are thermally conductive but electrically insulated, enhances heat dissipation efficiency by reducing thermal resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If integration density of electronic components is increased, then more components can be integrated into a given area, but heat dissipation becomes more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidheat dissipation
Core Design Contradiction:
Quantity of substanceVSTemperature

Solution Approach 1:

The patent divides the thermal management function into multiple segments by introducing thermal vias at different locations (first thermal via near the bonding interface, second thermal via away from the bonding interface) and using separate bonding pads (first bonding pad, second bonding pad) for different thermal paths. This segmentation allows heat to be dissipated through multiple independent channels, effectively managing heat from high-density integrated components.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from two-dimensional heat dissipation (surface level) to three-dimensional heat dissipation by introducing vertical thermal vias that extend through the substrate. The thermal vias create additional thermal conduction paths in the vertical dimension, allowing heat to escape from deeper within the package structure, thereby solving heat dissipation challenges associated with high integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Temperature

If thermal vias are introduced around the bonding interface, then heat dissipation efficiency is improved, but electrical interference may occur

Engineering Contradiction:
Improveheat dissipation efficiencyVSAvoidelectrical interference
Core Design Contradiction:
TemperatureVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the thermal conduction function from the electrical conduction path by introducing dedicated thermal vias that are electrically isolated from the bonding pads through insulating layers. The first thermal via is positioned between the first bonding pad and the first device, and the second thermal via is positioned between the second bonding pad and the second device, with insulating layers preventing electrical contact. This separation allows heat to be conducted away from the bonding interface without creating electrical interference or short circuits.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution effectively improves thermal control in integrated circuit packages by providing a thermal path while preventing electrical interference, thereby enhancing the performance and reliability of the devices.

Implementation Method 1

The introduction of thermal vias around the bonding interface between adjacent semiconductor dies, which are thermally conductive but electrically insulated, enhances heat dissipation efficiency by reducing thermal resistance.

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

The first insulator is between the first thermal via and the first die pad, electrically insulating the thermal via from the die pad while permitting thermal conduction.

Methodology Applied
Scientific EffectElectrical insulation: Electrical Resistance

Data Source

PatentUS20240379601A1Integrated circuit packages and methods of forming the same
Publication Date: 2024.11.14 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240379601A1 patent drawing
  • US20240379601A1 patent drawing
  • US20240379601A1 patent drawing

AI summary

An integrated circuit package includes first and second dies bonded to each other. The first die includes first die pads over a first device, first bonding pads over the first die pads, a first conductive via disposed between and electrically connected to a first one of the first die pads and a first one of the first bonding pads, and a first thermal via disposed between a second one of the first die pads and a second one of the first bonding pads and electrically insulated from the second one of the first die pads or the second one of the first bonding pads. The second die includes second bonding pads. The first one of the first bonding pads is connected to a first one of the second bonding pads. The second one of the first bonding pads is connected to a second one of the second bonding pads.