Die Package Structure with Embedded Trenches and Selective Etching

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Solution Overview

Problem

Conventional die packaging methods are time-consuming and face challenges with heat dissipation in power chips due to wire bonding, which complicates the process and limits the miniaturization and performance of die packages.

Innovation Solution

A method involving a conductive substrate with trenches, where dies are embedded, and a conductive layer is formed with selective etching to create bumps and electrodes, followed by an upper sealing layer to expose metal layers for electrical connections, omitting wire bonding and simplifying the process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional wire bonding is used to provide electrical connection for power chip, then electrical connection is achieved, but heat dissipation becomes difficult and process complexity increases

Engineering Contradiction:
Improveelectrical connectionVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts and removes the wire bonding process from the conventional packaging method. By using direct conductive connections through the substrate instead of wire bonding, the patent eliminates the complex wire bonding steps while maintaining electrical connection functionality, thereby reducing process complexity and improving heat dissipation.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical wire bonding system with a direct conductive connection system. Instead of using wires to connect electrical signals and power, the design uses conductive paths through the substrate itself, substituting a simpler conductive mechanism for the complex mechanical wire bonding process.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If conventional packaging process including die bonding, wire bonding and molding is used, then complete packaging is achieved, but manufacturing time is excessive

Engineering Contradiction:
Improvepackaging completenessVSAvoidmanufacturing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges multiple conventional packaging steps into a simplified process. By integrating the electrical connection function directly into the substrate structure and eliminating separate wire bonding and molding steps, the patent combines what were previously distinct operations into a more streamlined manufacturing process, reducing overall manufacturing time while maintaining packaging completeness.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by pre-integrating conductive paths into the substrate before die attachment. The conductive connections are prepared in advance within the substrate structure, eliminating the need for subsequent wire bonding operations and reducing the total number of manufacturing steps required.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If wire bonding is used for electrical connection, then electrical connectivity is provided, but heat dissipation of power chip is hindered

Engineering Contradiction:
Improveelectrical connectivityVSAvoidheat dissipation
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent replaces the wire bonding mechanical system with a direct conductive connection system that provides both electrical connectivity and thermal pathways. The conductive substrate structure serves dual functions of electrical connection and heat dissipation, eliminating the thermal barrier created by wire bonding while maintaining electrical functionality.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The conductive substrate structure performs multiple functions simultaneously: it provides electrical connection between dies and power chip, serves as a heat dissipation pathway for the power chip, and acts as the packaging structure itself. This multi-functionality eliminates the need for separate wire bonding and improves thermal management.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method simplifies the die packaging process, reduces heat dissipation issues, and enables miniaturization of die packages, improving their performance and manufacturing efficiency.

Implementation Method 1

By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes

Methodology Applied
Scientific EffectSelective etching:

Implementation Method 2

forming the conductive layer includes forming a copper seed layer by using electroless plating and forming a copper plating layer on the copper seed layer by using electroplating

Methodology Applied
Scientific EffectElectroless plating:

Implementation Method 3

forming the conductive layer includes forming a copper seed layer by using electroless plating and forming a copper plating layer on the copper seed layer by using electroplating

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11302664B2Method of manufacturing die package structure
Publication Date: 2022.04.12 COMCHIP TECH
  • US11302664B2 patent drawing
  • US11302664B2 patent drawing
  • US11302664B2 patent drawing

AI summary

A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.