Die Package Structure With Vertical Wires for Warpage Control

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Solution Overview

Problem

Existing methods for forming bumps and bump pads on singulated semiconductor dies are inefficient, leading to warpage issues and high costs due to the need for two carrier substrates and difficulty in controlling die warpage during the flip chip packaging process.

Innovation Solution

A method involving disposing dies on a carrier substrate with signal junctions facing up, forming vertical wires, a supporting dielectric layer, redistribution traces, and bumps, which reduces warpage and manufacturing costs by maintaining the carrier substrate during high-temperature processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If existing methods dispose semiconductor dies on a carrier substrate and perform bumping process, then bumps and bump pads can be formed on singulated dies, but warpage control becomes difficult and two carrier substrates are required at high cost

Engineering Contradiction:
Improvebump formation capabilityVSAvoidcarrier substrate requirement
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines the bump formation process with the singulated die structure by integrating vertical wires, supporting dielectric layer, redistribution traces, and bumps directly onto the singulated die. This merging eliminates the need for separate carrier substrates while maintaining the capability to form bumps and bump pads, thereby reducing device complexity and manufacturing cost.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent performs preliminary actions by forming vertical wires, supporting dielectric layer, and redistribution traces on the singulated die before the actual bump formation process. This preliminary structuring enables subsequent bump formation without requiring additional carrier substrates, resolving the contradiction between manufacturing ease and device complexity.

Inventive Principle:
Principle #10Preliminary action

2Ease of manufacture

If existing technology uses two carrier substrates for bumping process, then bumps can be formed on singulated dies, but manufacturing cost increases

Engineering Contradiction:
Improvebump formation capabilityVSAvoidcarrier substrate quantity
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent extracts and eliminates the unnecessary carrier substrate from the bump formation process. By integrating all required structures (vertical wires, supporting dielectric layer, redistribution traces, and bumps) directly onto the singulated die, the method removes the requirement for two carrier substrates, thereby reducing the quantity of materials needed and lowering manufacturing cost.

Inventive Principle:
Principle #2Taking out (Extraction)

3Ease of manufacture

If existing methods perform bumping on disposed dies, then bump pads can be formed, but warpage control becomes difficult

Engineering Contradiction:
Improvebump pad formationVSAvoidwarpage control
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces a supporting dielectric layer as an intermediary between the singulated die and the bump formation process. This supporting dielectric layer provides mechanical support and stability during the formation of vertical wires, redistribution traces, and bumps, thereby enabling precise warpage control while maintaining ease of manufacture for bump pad formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20240274565A1Die package structure and method for forming the same
Publication Date: 2024.08.15 WINBOND ELECTRONICS CORP
  • US20240274565A1 patent drawing
  • US20240274565A1 patent drawing
  • US20240274565A1 patent drawing

AI summary

A method for forming a die package structure, including disposing a plurality of dies on a carrier substrate, wherein the top surface of each die has a plurality of signal junctions. The method also includes forming a vertical wire on each of the signal junctions, forming a supporting dielectric layer on the carrier substrate, wherein the supporting dielectric layer covers the dies and exposes the top of the vertical wires, and forming a plurality of redistribution traces on the supporting dielectric layer, wherein the redistribution traces are electrically connected to each of the vertical wires. The method further includes forming a bump at the bonding site of each of the redistribution traces, and performing a cutting process to singulate the dies.