Die Pad Surface Roughness and Hollow Structure for Semiconductor Reliability

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Solution Overview

Problem

The reliability of semiconductor devices with tab exposure type packaging is compromised due to the ease of exfoliation of the sealed body from the die pad, which increases with the larger plane area of the die pad, leading to deterioration in heat dissipation and electrical coupling reliability.

Innovation Solution

A manufacturing method for semiconductor devices that involves forming a die pad with a larger plane area than the semiconductor chip, featuring a bonding process with a coarser surface roughness on the upper surface and hollow part arrangements to inhibit exfoliation, along with a stepped and grooved undersurface to prevent resin burr formation and moisture invasion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If the plane area of the die pad is made larger to improve heat dissipation and electrical coupling, then heat radiation area is increased, but exfoliation of the sealed body becomes easier and reliability deteriorates

Engineering Contradiction:
Improveheat dissipationVSAvoidexfoliation resistance
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The die pad surface is designed with different roughness characteristics in different regions: the first surface (bonding surface) has coarser roughness to enhance adhesion and prevent exfoliation, while the second surface (exposed surface) has smoother finish. This local differentiation allows the die pad to simultaneously achieve large area for heat dissipation and sufficient adhesion strength to prevent sealed body exfoliation.

Inventive Principle:
Principle #3Local quality

2Reliability

If grooves or holes are formed in the hollow part arrangement area to prevent exfoliation, then adhesion is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveexfoliation resistanceVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The hollow part arrangement area incorporates grooves or holes that create a porous structure on the die pad surface. This porous structure increases the surface area and mechanical interlocking capability between the die pad and sealed body, significantly improving exfoliation resistance. The grooves or holes are strategically positioned in the hollow part arrangement area to optimize adhesion without excessive manufacturing complexity.

Inventive Principle:
Principle #31Porous materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method enhances the reliability of semiconductor devices by preventing exfoliation and improving heat dissipation and electrical coupling by maintaining the adhesion between the die pad and the sealed body, while also minimizing moisture invasion and resin burr formation.

Implementation Method 1

surface roughness of the first plane is made coarser than surface roughness of the second plane

Methodology Applied
Scientific EffectAdhesion: Adhesive

Data Source

PatentUS9741641B2Method for manufacturing semiconductor device, and semiconductor device
Publication Date: 2017.08.22 RENESAS ELECTRONICS CORP
  • US9741641B2 patent drawing
  • US9741641B2 patent drawing
  • US9741641B2 patent drawing

AI summary

A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.