Die Pad Thickness Structure for SiC Chip Peeling Resistance
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Solution Overview
Problem
Semiconductor devices with semiconductor chips fixed on die pads using connection layers like solder face reliability issues due to chip peeling at connection portions caused by temperature changes, leading to altered device characteristics.
Innovation Solution
The semiconductor device design includes a die pad with a thinner peripheral region surrounding a thicker central region, a semiconductor chip with a silicon carbide layer positioned on the inner side of the die pad, and a connection layer between the chip and the die pad, which reduces stress and peeling likelihood.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a connection layer is used to fix the semiconductor chip on the die pad, then the electrical connection is established, but the chip may peel off due to temperature changes causing reliability issues
Solution Approach 1:
The die pad is designed with a thickness difference between the first region (under the chip) and the second region (peripheral area), creating local structural variation. The first region has greater thickness to provide enhanced support and reduce stress concentration at the connection interface, thereby improving peel resistance without affecting overall device structure
Solution Approach 2:
The connection layer is positioned in advance between the lower electrode and the die pad surface to provide stress absorption before thermal cycling occurs. This pre-positioned connection layer acts as a cushioning element that accommodates thermal expansion differences and prevents direct stress transmission to the chip-die pad interface
2Ease of manufacture
If the semiconductor chip is positioned on the die pad, then the device structure is formed, but stress concentration occurs at the connection portion during temperature changes
Solution Approach 1:
The die pad features a localized thickness variation with the first region being thicker than the second region. This local structural enhancement is positioned specifically under the semiconductor chip to provide stress distribution without complicating the overall manufacturing process or device assembly
Solution Approach 2:
The die pad structure is designed asymmetrically with respect to thickness distribution, where the first region has greater thickness than the second region. This asymmetric design creates a stress-absorbing structure that accommodates thermal expansion differences while maintaining simple manufacturing procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively suppresses semiconductor chip peeling, thereby enhancing the reliability of the semiconductor device by reducing stress at the connection portion.
Implementation Method 1
when the semiconductor chip is peeled off at the connection portion due to temperature changes during the use of the semiconductor device
Data Source
AI summary
A semiconductor device of embodiments includes: a die pad including a first region and a second region surrounding the first region and thinner than the first region; a semiconductor chip including an upper electrode, a lower electrode, and a silicon carbide layer between the upper electrode and the lower electrode and provided on an inner side rather than the second region on a surface of the die pad; and a connection layer for connecting the lower electrode to the surface.