Die Pair Temperature Sensor Layout for SoC Hotspot Tracking
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Solution Overview
Problem
In managing the temperature of complex systems on chip (SoCs), large thermal sensors consume significant silicon area, forcing them to be placed away from hotspots, which reduces operating frequency and performance due to design margin requirements.
Innovation Solution
Implementing a die pair topology where thermal sensors are placed in close planar proximity to hotspots on a base die, allowing accurate temperature tracking without being on the top die, thereby enabling higher operating frequencies and performance without design margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If large thermal sensors are placed at the hottest parts of the die to accurately measure worst-case temperature, then measurement precision is improved, but the critical logic needs to be significantly spaced out, worsening productivity
Solution Approach 1:
The patent moves the temperature sensor from the traditional 2D plane of the die to a 3D stacked configuration by placing the sensor on a separate die that is vertically integrated with the compute engine die. This allows the sensor to be positioned in close proximity to hot spots without consuming lateral silicon area, thus avoiding logic spacing requirements while maintaining accurate temperature measurement.
Solution Approach 2:
The patent divides the system into multiple independent dies: one die for the compute engine logic and another die for the temperature sensor. This segmentation allows each component to be optimized independently - the compute engine can maintain dense logic placement for high performance while the sensor is placed optimally for accurate temperature measurement near hot spots.
2Productivity
If thermal sensors are spaced farther away from hot spots to avoid spacing out logic, then productivity is improved, but the extra temperature difference to the hottest part of the die reduces operating frequency at a fixed voltage or power
Solution Approach 1:
By transitioning to 3D stacked architecture, the sensor can be positioned vertically close to hot spots without lateral spacing constraints. This eliminates the trade-off between sensor proximity and logic density, allowing the sensor to accurately measure peak temperatures while the compute engine maintains high operating frequency without temperature margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate peak temperature tracking on the top die without sensors, maintaining high operating frequency and performance by judiciously placing sensors on the base die, avoiding the adverse effects of monolithic designs.
Implementation Method 1
a temperature sensor placed in a transistor layer of the base die in close planar proximity to at least one hot spot location in an additional transistor layer of the compute engine die
Data Source
AI summary
A method for die pair partitioning can include providing a first circuit die having a first metal stack. The method can additionally include positioning a second circuit die having a second metal stack in a manner that places a temperature sensor in a transistor layer of the second circuit die in planar proximity to at least one hot spot located in an additional transistor layer of the first circuit die. The method can also include connecting the first metal stack of the first circuit die to the second metal stack of the second circuit die. Various other methods, systems, and computer-readable media are also disclosed.