Semiconductor Die ROI Alignment Across Multiple Imaging Tools

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Solution Overview

Problem

Existing fault analysis tools for semiconductor dies face challenges in efficiently and accurately locating regions of interest (ROIs) across multiple imaging techniques due to image variability and the need for manual database consultation, which is time-consuming and prone to human error.

Innovation Solution

A die assessment circuitry that utilizes pattern recognition to automatically locate ROIs by determining a pattern of fiducial markers across different imaging tools, eliminating the need for manual database access and reducing human intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If manual database consultation is used to locate ROIs across multiple imaging tools, then flexibility in handling different imaging techniques is maintained, but time consumption increases and human error occurs

Engineering Contradiction:
Improveaccuracy of ROI locationVSAvoidtime for manual database consultation
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs self-alignment by automatically comparing fiducial marker patterns across images from different imaging tools and computing transformation parameters without requiring manual database consultation. The die assessment circuitry independently locates ROIs by processing the images and identifying fiducial markers, eliminating the need for operator intervention in database lookup and alignment procedures.

Inventive Principle:
Principle #25Self-service

2Adaptability or versatility

If multiple imaging tools are used to analyze semiconductor dies, then comprehensive fault detection capability is improved, but image variability and alignment complexity increase

Engineering Contradiction:
Improvefault detection capabilityVSAvoidalignment complexity across imaging tools
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Fiducial markers serve as intermediary reference features that bridge images from different imaging tools. The system detects these markers in each image, uses them to compute transformation parameters (rotation, translation, scaling), and applies these transformations to align all images to a common coordinate system, thereby simplifying the integration of multiple imaging tools.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system changes the parameter set used for alignment by relying on fiducial marker coordinates rather than attempting to directly align complex semiconductor structures. By extracting and comparing the positions of fiducial markers across images, the system computes transformation parameters that simplify the alignment process and accommodate variations between different imaging tools.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If automated pattern recognition is implemented to locate ROIs, then processing speed and accuracy improve, but the complexity of the analysis system increases

Engineering Contradiction:
Improvespeed of ROI identificationVSAvoidcomplexity of pattern recognition system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

Fiducial markers are pre-placed on the semiconductor die at known locations before imaging. This preliminary action creates easily identifiable reference features that guide the automated pattern recognition process. The die assessment circuitry uses these pre-existing markers to quickly establish coordinate systems and locate ROIs without needing to interpret complex semiconductor structures from scratch.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4718377A1Methods and apparatus for semicondcutor die fault analysis using multiple imaging tools
Publication Date: 2026.04.01 INTEL CORP
  • EP4718377A1 patent drawingFigure 1~2
  • EP4718377A1 patent drawingFigure 3
  • EP4718377A1 patent drawingFigure 4A~4C

AI summary

Methods and apparatus for semiconductor die fault analysis are disclosed. An example apparatus comprises interface circuitry, machine-readable instructions, and at least one processor circuit to be programmed by the machine-readable instructions to identify a location of a reference feature on a semiconductor die within a first image of the semiconductor die, the first image containing a region of interest on the semiconductor die adjacent to the reference feature, transform a baseline pattern of the semiconductor die to align a location of a baseline feature in the baseline pattern with the location of the reference feature in the first image, and determine a location of the region of interest in the first image based on the transformed baseline pattern.