Die Scale Strain Gauge for IC Chip Mapping
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Solution Overview
Problem
Existing strain gauges are not suitable for measuring strains at the integrated circuit die level due to their complexity, unsuitability for vertical strain measurement, and interference with intrinsic electronic components, and cannot easily be applied to the hidden chip within a package.
Innovation Solution
A resistive, metallic strain gauge system with serpentine patterns is deployed on the chip's top and buried layers, using a Kelvin or Wheatstone bridge configuration to measure strain across multiple dimensions without interfering with existing circuitry, allowing for precise strain mapping on both surfaces and within the chip's depth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional strain gauges are used to measure strain on integrated circuit dies, then strain measurement capability is provided, but the gauges are unsuitable for die-level application and interfere with intrinsic electronic components
Solution Approach 1:
The patent applies local quality by creating strain gauge structures specifically adapted to the die level with dimensions and configurations matched to integrated circuit geometries. The strain gauges are designed with local characteristics (size, pattern, material properties) that enable them to function at the die level without interfering with electronic components, while maintaining strain measurement capability.
Solution Approach 2:
The patent extracts the strain measurement function from traditional bulky strain gauges and implements it using minimal structures that can be integrated at the die level. By taking out only the essential measurement functionality and removing unnecessary complexity, the strain gauges become suitable for application on integrated circuit dies without interfering with intrinsic electronic components.
2Measurement precision
If diffusion-based strain measuring devices are used on chips, then strain measurement is enabled, but complex circuitry is formed that adversely affects strain measurements
Solution Approach 1:
The patent extracts the strain measurement function from complex diffusion-based devices and implements it using simple metallic resistive structures. By removing the unnecessary complex circuitry (diodes, transistors, capacitors) and retaining only the essential resistive element that changes with strain, the measurement device becomes simpler while maintaining or improving measurement accuracy.
Solution Approach 2:
The patent uses simple metallic resistive structures instead of complex semiconductor devices. These simpler structures are easier to fabricate, less prone to introducing measurement errors, and can be integrated into the chip fabrication process without requiring complex additional processing steps.
3Measurement precision
If standard diffusion methods are used to form strain measuring elements, then strain measurement is possible, but fabrication complexity equals that of full integrated circuit fabrication
Solution Approach 1:
The patent merges the strain gauge fabrication process with the existing integrated circuit metallization process. By combining the strain gauge formation with standard chip fabrication steps (metal deposition, patterning), the strain gauges are created as an integrated part of the chip manufacturing process without requiring separate complex fabrication steps, thereby improving ease of manufacture.
Solution Approach 2:
The patent makes the standard IC fabrication process multi-functional by using it to create both the electronic circuitry and the strain measurement structures. The same metallization layers and patterning processes that create functional circuit elements are also used to create the strain-sensitive resistive elements, eliminating the need for specialized strain gauge fabrication equipment and processes.
4Measurement precision
If semiconductor strain gauges are used, then strain measurement on chip is achieved, but they cannot easily measure vertical strain of integrated circuit
Solution Approach 1:
The patent applies dimensionality change by designing strain gauge structures that extend through multiple layers and depths of the integrated circuit. By using vertical vias, multi-layer metallization, and three-dimensional resistive patterns, the strain gauges can detect strain components in vertical directions in addition to horizontal directions, providing comprehensive strain measurement capability in all spatial dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate and non-intrusive strain measurement across the entire integrated circuit chip, including vertical strains, without affecting the chip's functionality and simplifying the fabrication process, thus improving production yield by identifying and mitigating strain-related failures.
Implementation Method 1
As stresses on the article cause it to distort or change its physical shape, the attached strain gauge changes its physical dimensions and thus its resistance. The resistance change of the strain gauge is correlated to strains in the surface.
Data Source
AI summary
A chip with resistive, metallic strain gauges distributed on surfaces on and buried within the chip. Also, vertically arranged vias and vertical thin film resistive strain gauges are described. The resistive strain gauges can be multiplexed wherein strain can be measured across the topology of the chip in each of the top, bottom and buried layers and any vertical strain. The resistive strain gauges may be in serpentine patterns and may be arranged on via or on vertical edges of grooves that extend from an upper or lower surface of the chip to buried layers. In this fashion, the distributed strain gauges may be used to map the strain throughout the body of a chip. A Kelvin bridge may be used to measure the strain, but other such measuring techniques and devices may be used.