Semiconductor Die Seal-Ring Dicing to Prevent Silicon Debris

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Solution Overview

Problem

The miniaturization of display ICs leads to insulation issues due to reduced pitch between wirings, causing defects such as cracks and short circuits during the blade dicing process, particularly due to the generation of silicon debris and burrs in semiconductor devices.

Innovation Solution

A method involving the formation of an interlayer dielectric layer, metal pads, and a passivation dielectric layer, where plasma etching is used to expose the substrate and metal pads, followed by mechanical sawing to remove the scribe line region, thereby preventing the generation of silicon debris and burrs, and minimizing mechanical stress on the active region.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If blade dicing is used to cut the substrate, then the scribe line region can be removed, but silicon debris and burrs are generated that cause short circuits and defects

Engineering Contradiction:

Improvedicing efficiencyVSAvoidsilicon debris and burrs

Core Design Contradiction:

ProductivityVSObject-generated harmful factors

Solution Approach 1:

The method performs preliminary etching of the interlayer dielectric layer and passivation dielectric layer in the scribe line region before dicing. This creates grooves that prevent silicon debris and burrs from being generated and transferred to the device region during subsequent blade dicing, thus eliminating the harmful effects while maintaining efficient dicing

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The method converts the potentially harmful blade dicing process into a beneficial one by first creating protective grooves through etching. The mechanical energy of blade dicing that would normally generate harmful silicon debris is redirected to cleanly cut along the pre-formed grooves, transforming the harmful dicing process into a clean separation process

Inventive Principle:

Principle #22Blessing in disguise (Convert harm into benefit)

2Volume of moving object

If the pitch between wirings is reduced for miniaturization, then the IC size is reduced, but insulation becomes problematic leading to short circuits

Engineering Contradiction:

ImproveIC sizeVSAvoidinsulation

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The method segments the substrate into distinct functional regions (device region, scribe line region, seal-ring region) with clear boundaries. By etching the scribe line region separately and creating physical grooves, it prevents contamination from the scribe line from affecting the device region, thereby maintaining insulation reliability even with reduced wiring pitch

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The method extracts and removes the scribe line region material through preliminary etching before dicing. This extraction prevents silicon debris from the scribe line from contaminating the device region, ensuring insulation integrity is maintained despite miniaturization that reduces wiring pitch

Inventive Principle:

Principle #2Taking out (Extraction)

3Object-generated harmful factors

If plasma etching is performed to remove the interlayer dielectric layer, then silicon debris generation is prevented, but additional process steps are required

Engineering Contradiction:

Improvesilicon debrisVSAvoidprocess steps

Core Design Contradiction:

Object-generated harmful factorsVSDevice complexity

Solution Approach 1:

The method merges the interlayer dielectric layer removal function with the scribe line region preparation for dicing. By performing plasma etching on the interlayer dielectric layer in the scribe line region, it simultaneously removes the dielectric material and creates grooves that prevent silicon debris generation, combining multiple functions into one process step

Inventive Principle:

Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents defects like short circuits and silicon debris generation, reducing the defect rate of semiconductor dies by maintaining the integrity of the interlayer dielectric layers during the dicing process.

Implementation Method 1

first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process

Methodology Applied

Scientific EffectPlasma etching: Plasma

Data Source

PatentUS11887892B2Method for forming semiconductor die with die region and seal-ring region

Publication Date: 2024.01.30 MAGNACHIP SEMICON LTD

AI summary

A method for forming a semiconductor die, includes forming an interlayer dielectric layer on a substrate having a semiconductor die region, a seal-ring region, and a scribe line region, forming a metal pad and a test pad on the interlayer dielectric layer, forming a passivation dielectric layer on the interlayer dielectric layer, the metal pad, and the test pad, first etching the passivation dielectric layer and the interlayer dielectric layer existing between the seal-ring region and the scribe line region to a predetermined depth using a plasma etching process, second etching the passivation dielectric layer to expose the metal pad and the test pad, forming a bump on the metal pad, and dicing the substrate while removing the scribe line region by mechanical sawing.