Die Seal Ring Fin Structure for CMP Collapse Prevention

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Solution Overview

Problem

Conventional die seal rings are insufficient in protecting active regions of micro-processor chips due to shrinking line widths and are prone to collapse during chemical mechanical polishing (CMP) processes, particularly in FINFET manufacturing.

Innovation Solution

A die seal ring with a substrate and a first layer featuring a stamp-like fin ring structure is introduced, which is formed simultaneously with the fin structure of the Fin-FET using a sidewall image transfer process, providing enhanced rigidity and protection by encompassing the active region with a closed or open 'saw-tooth', 'zigzag', or 'serpent' design.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If the die seal ring width is reduced to accommodate shrinking line widths, then the chip area is optimized, but the protective capability of the die seal ring deteriorates and it becomes prone to collapse during CMP processes

Engineering Contradiction:
Improvechip areaVSAvoidprotective capability of die seal ring
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The die seal ring is segmented into multiple discrete fins arranged in a circular pattern, forming a fin ring structure. This segmentation allows the seal ring to maintain protective functionality while occupying less overall area, as the fins provide structural support and protection through their distributed arrangement rather than requiring a continuous wide structure

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The die seal ring transitions from a planar two-dimensional structure to a three-dimensional fin ring structure with vertical fins extending from the substrate. This dimensional change provides enhanced mechanical strength and protection against CMP collapse while maintaining a compact footprint, as the vertical fins add structural rigidity without increasing the horizontal area occupied

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If a conventional die seal ring structure is used, then the manufacturing process is simple, but the structural integrity and resistance to stress-induced damage during manufacturing is insufficient

Engineering Contradiction:
Improvemanufacturing process simplicityVSAvoidstructural integrity of die seal ring
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The formation of the die seal ring fins is merged with the existing FinFET fin formation process. Both structures are created simultaneously using the same spacer-based sidewall image transfer methodology, eliminating the need for separate fabrication steps while achieving enhanced structural integrity through the fin ring configuration

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The spacer structure serves dual purposes: it defines the FinFET fin geometry and simultaneously defines the die seal ring fin geometry. The sacrificial spacer is self-removed after serving its patterning function, and the resulting fin structures self-align without requiring additional alignment steps, maintaining manufacturing simplicity while improving structural strength

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS9048246B2Die seal ring and method of forming the same
Publication Date: 2015.06.02 MARLIN SEMICON LTD
  • US9048246B2 patent drawing
  • US9048246B2 patent drawing
  • US9048246B2 patent drawing

AI summary

A die seal ring is provided. The die seal ring includes a substrate and a first layer extruding from the substrate. The first layer has a first fin ring structure and a layout of the first fin ring structure has a stamp-like shape. In addition, a method for forming a die seal ring is provided. A substrate having an active region is provided. A patterned sacrificial layer is formed on the substrate. A spacer is formed on the sidewall of the patterned sacrificial layer. The patterned sacrificial layer is removed. The substrate is patterned by using the spacer as a mask, thereby simultaneously forming at least a fin structure of a Fin-FET and a first layer of the die seal ring.