Die-to-Die Serializer Clocking for Accurate 2.5D Data Links
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Solution Overview
Problem
In 2.5D semiconductor packaging technology, efficiently providing proper clock rates for serializer and de-serializer stages to ensure accurate data serialization and de-serialization between integrated circuit dies is a challenge.
Innovation Solution
A communication interface circuit between two dies using a serializer and a de-serializer, connected via an interposer or redistribution layer, with separate clocks generated for each stage to manage data transmission, ensuring proper clock phase alignment for accurate de-serialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clocks are provided for serializer and de-serializer stages, then data transmission accuracy is improved, but device complexity increases
Solution Approach 1:
The clock generation is segmented into multiple independent clock domains: a first clock for the serializer stage and a second clock for the de-serializer stage. This segmentation allows each stage to operate with optimally tuned clock frequencies, improving data transmission accuracy while maintaining manageable complexity through modular clock management.
Solution Approach 2:
A clock generator acts as an intermediary component that provides synchronized clock signals to both serializer and de-serializer stages. This intermediary manages the clock distribution and phase alignment, ensuring accurate data transmission without requiring complex clock management within each individual stage.
2Productivity
If multiple clock rates are used for different stages, then serialization and de-serialization efficiency is improved, but clock synchronization difficulty increases
Solution Approach 1:
The system dynamically adjusts clock rates for different stages based on their specific requirements. The serializer operates at one clock rate optimized for data encoding, while the de-serializer operates at another rate optimized for data recovery. This dynamic clock rate adjustment improves serialization efficiency while the clock generator maintains phase alignment through coordinated clock distribution.
Data Source
AI summary
A circuit of communication interface between dies is provided. The circuit includes a first interface of the first die having a serializer to serialize an input data of N bits a serialized data for transmitting out and a second interface of the second die having a de-serializer to receive and deserialize the serialized data into a de-serialized data. In addition, an interconnection structure connected between the first die and the second die to connect the serializer and the de-serializer, wherein the interconnection structure is an interposer or a redistribution layer of a semiconductor structure to form a parallel bus for transmitting the serialized data in one line of the parallel bus between the first die and the second die. A clock generator provides a first clock to a first ripple counter of the serializer and a second clock to a second ripple counter of the de-serializer.