Semiconductor Die Shift Compensation in Wafer-Level Packaging
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Solution Overview
Problem
Semiconductor die movement during packaging leads to alignment issues and reduced yields in wafer-level packaging, causing misalignment of subsequent material layers and potential electrical shorting due to non-uniform stress and deformation of insulating materials.
Innovation Solution
Implementing an overlay metrology apparatus to measure and correct the position of semiconductor dies on a temporary carrier before encapsulation, and using shift metrology to adjust for non-linear displacement during the encapsulation process, ensuring accurate alignment and compensation during the formation of redistribution layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If semiconductor dies are positioned on carrier wafers and insulating material is formed to cover them, then wafer-level packaging is achieved, but undesirable movement of semiconductor dies occurs causing alignment problems
Solution Approach 1:
The patent applies preliminary action by forming a release layer on the carrier wafer before positioning the semiconductor dies. This release layer is prepared in advance to control the bonding and subsequent release of dies, preventing movement during packaging while enabling precise alignment. The layer is formed with specific properties (thickness, material composition) before the dies are placed, ensuring stability during the encapsulation process.
Solution Approach 2:
The release layer acts as an intermediary between the carrier wafer and the semiconductor dies. It mediates the interaction by providing a controlled bonding interface that holds dies in place during packaging but allows for release when needed. This intermediary layer resolves the contradiction by enabling both secure positioning (preventing movement) and controlled release (maintaining alignment precision).
2Reliability
If insulating material is formed to cover semiconductor dies, then encapsulation is achieved, but non-uniform stress and deformation occur causing electrical shorting
Solution Approach 1:
The patent applies parameter changes by carefully controlling the thickness, material composition, and physical properties of the release layer. By adjusting these parameters, the layer can accommodate stress during encapsulation without transmitting non-uniform stress to the semiconductor dies. The release layer's parameters are optimized to prevent deformation that would lead to electrical shorting, while still providing adequate support for encapsulation.
3Manufacturing precision
If overlay metrology apparatus is used to measure and correct die positions, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex mechanical alignment systems with a more simplified approach using release layer control. Instead of relying on sophisticated metrology apparatus to measure and correct every die position, the release layer is designed to inherently maintain alignment during the packaging process. This substitution reduces device complexity while achieving the necessary alignment precision through material science rather than complex mechanical measurement systems.
Data Source
AI summary
A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.