Semiconductor Die Sidewall Passivation After Singulation
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Solution Overview
Problem
Semiconductor chips are vulnerable to chemical and environmental interactions due to unprotected sidewalls during the backend assembly process, leading to potential chip failure and limited material options for packaging, which complicates high-temperature module operations.
Innovation Solution
A method involving a passivation layer is applied to the semiconductor chip sidewalls after singulation, using deposition processes at low temperatures to protect the chips before backend processes, ensuring compatibility with various materials and environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the wafer is singulated to generate individual dies, then the dies can be processed and mounted separately, but the sidewalls of the dies become unprotected and vulnerable to chemical and environmental interactions
Solution Approach 1:
The patent applies a passivation layer to the sidewalls of the dies before they are mounted in the backend assembly process. This preliminary protective action prevents chemical interactions between the exposed silicon sidewalls and backend materials such as solder, potting compounds, and housing materials, thereby maintaining chip reliability while still enabling separate processing and mounting of individual dies.
2Reliability
If packaging materials are selected to be compatible with unprotected chip sidewalls, then chip failure from chemical interactions is avoided, but material options are limited and cost increases
Solution Approach 1:
The passivation layer acts as an intermediary barrier between the chip sidewalls and the packaging materials. This intermediate layer allows the use of a broader range of packaging materials including cost-effective options like standard solder alloys and potting compounds, while preventing direct harmful interactions with the silicon sidewalls. The passivation layer enables material versatility without compromising chip reliability.
3Temperature
If module operation temperature is increased, then performance requirements are met, but the risk of negative impact on chip performance increases due to unprotected sidewalls
Solution Approach 1:
The passivation layer provides preliminary protection against thermal and chemical degradation at elevated temperatures. By preventing direct exposure of the silicon sidewalls to high-temperature processing and operation environments, the passivation layer maintains chip performance stability and reliability even when module operation temperatures are increased to meet performance requirements.
4Stability of the object's composition
If deposition process temperature is kept below the melting temperature of the auxiliary carrier, then the auxiliary carrier integrity is maintained, but the passivation layer must be deposited at lower temperatures which may affect deposition quality
Solution Approach 1:
The patent employs deposition processes operated at temperatures below the melting point of the auxiliary carrier (typically polymer tape). By optimizing deposition parameters such as pressure, gas flow, and deposition rate, high-quality passivation layers are achieved at these reduced temperatures without compromising the auxiliary carrier integrity. This parameter optimization enables simultaneous maintenance of both carrier stability and deposition quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The passivation layer provides effective protection against chemical interactions and environmental influences, enabling the use of new materials and processes, enhancing chip robustness and facilitating second-source material integration while maintaining bondability and solderability.
Implementation Method 1
covering at least the side surfaces of the dies with a passivation layer using a deposition process
Data Source
AI summary
A method of manufacturing a semiconductor package is provided. The method may include singulating a wafer including a plurality of dies fixed to an auxiliary carrier to generate dies having released side surfaces, covering at least the side surfaces of the dies with a passivation layer using a deposition process at a temperature below the melting temperature of the auxiliary carrier, keeping a gap between the passivation layers at the side surfaces of adjacent dies of the plurality of dies.