Die-to-Die Slice Deskewing With FIFO Read Pointer Alignment
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Solution Overview
Problem
In System on a Chip (SoC) devices, clock and data transmission between chiplets experience skew variations due to process, temperature, and voltage fluctuations, leading to misalignment and erroneous operations.
Innovation Solution
A die-to-die interface with a transmission interface and receive circuitry that uses first-in, first-out (FIFO) buffers and skew controllers to synchronize data across slices, adjusting read pointers based on clock signal differences to align data transmission paths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If separate transmission paths are used for different slices, then data can be transmitted in parallel, but skew variations cause misalignment between slices
Solution Approach 1:
The patent divides the data transmission system into multiple independent slices, each with its own transmission path and FIFO buffer. This segmentation allows parallel transmission while enabling independent skew compensation for each slice through dedicated deskew logic that adjusts read pointers based on measured skew values.
Solution Approach 2:
The patent dynamically adjusts the read pointer position in each FIFO buffer based on measured skew variations. By changing the timing parameter (read pointer offset) for each slice according to its specific skew characteristics, the system compensates for path variations and achieves aligned data output across all slices.
2Manufacturing precision
If FIFO buffers are used to compensate for skew, then data alignment is improved, but power consumption and FIFO depth requirements increase
Solution Approach 1:
The patent applies skew compensation only when necessary by measuring skew variations and activating deskew logic proportionally to the measured skew magnitude. The read pointer adjustment is precisely calibrated to match the actual skew value, avoiding excessive FIFO depth requirements and unnecessary power consumption from over-compensation.
Solution Approach 2:
The patent implements a feedback mechanism where skew is measured between corresponding data samples from different slices, and this measurement is used to dynamically adjust read pointers in real-time. This closed-loop control ensures minimal FIFO depth is used while maintaining data alignment, reducing both power consumption and buffer requirements.
3Manufacturing precision
If skew compensation logic is added, then data alignment between slices is improved, but device complexity increases
Solution Approach 1:
The patent extracts the skew compensation function into a separate, modular deskew logic block that operates independently for each slice. This extracted module contains only the essential functionality (read pointer adjustment based on skew measurement), simplifying the overall design while achieving the alignment goal.
Solution Approach 2:
The patent implements a universal deskew logic template that can be replicated for each slice, where the same basic structure (skew measurement, read pointer adjustment) serves multiple purposes across different slices. This modular universal approach reduces design complexity compared to custom solutions for each slice.
Data Source
AI summary
A die-to-die (D2D) interface between chiplets of a system on a chip (SoC) in which each of the chiplets are subdivided into slices. The D2D interface includes a transmission interface coupled between first and second chiplets, which includes a first transmission path for a first slice and a second transmission path for a second slice. The first chiplet includes receive circuitry which further includes a write interface and a read interface. The write interface stores data received from the first transmission path into a first FIFO using a first clock signal received via the first transmission path, and stores data received from the second transmission path into a second FIFO using a second clock signal received via the second transmission path. The read interface reads data stored in the first and second FIFOs using the first clock signal. The first and second transmission paths may be subject to different delays.